databuffer.vhd

buffer for in/out data.

library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity DATABUFFER is
port(	
		CLOCK_50: IN STD_LOGIC;
		SW: in std_logic_vector(9 downto 0);
		LEDR: out std_logic_vector(9 downto 0);
		LEDG: out std_logic_vector(7 downto 0);
		KEY: in std_logic_vector(3 downto 0)
	);
end DATABUFFER;

architecture struct of DATABUFFER is

component data_buffer
port(
	wen: in std_logic;
	oen: in std_logic;
	raddress: in std_logic_vector(7 downto 0);
	waddress: in std_logic_vector(7 downto 0);
	datain: in std_logic_vector(7 downto 0);
	dataout: out std_logic_vector(7 downto 0)
	);
end component;

COMPONENT ClockGen
port(	clk_source: in std_logic;
		clk_1Mhz: out std_logic;
		clk_100Khz: out std_logic;
		clk_10Khz: out std_logic;
		clk_1Khz: out std_logic;
		clk_100Hz: out std_logic;
		clk_10Hz: out std_logic;
		clk_1Hz: out std_logic
	);
end COMPONENT;

SIGNAL WRITEBUFF	: STD_LOGIC := '1';
SIGNAL WEN			: STD_LOGIC := '0';
SIGNAL COUNT		: INTEGER RANGE 0 TO 255 := 0;
SIGNAL ADDRESS		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DATA			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLOCK		: STD_LOGIC;

begin
	PROCESS(CLOCK)
	BEGIN
		IF (CLOCK'EVENT AND CLOCK = '1') THEN
			IF (WRITEBUFF = '1') THEN
				IF (COUNT < 251) THEN
					ADDRESS <= CONV_STD_LOGIC_VECTOR(COUNT, 8);
					DATA	<= CONV_STD_LOGIC_VECTOR(COUNT, 8);
					COUNT	<= COUNT + 1;
				ELSE
					WRITEBUFF <= '0';
				END IF;
			END IF;
		END IF;
		WEN	<= NOT CLOCK;
	END PROCESS;
	
	SI: ClockGen
		PORT MAP(
			clk_source	=> CLOCK_50
--			clk_100hz	=> CLOCK
			);
	CLOCK <= CLOCK_50;
	b: data_buffer port map (
				wen => WEN,
				oen => CLOCK,
				raddress => SW(7 downto 0),
				waddress => ADDRESS,
				datain => DATA,
				dataout => LEDG
			);
	LEDR(0) <= CLOCK;
end struct;