📄 datasource.vhd.bak
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--use WORK.addreload.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY datasource IS
port(
clk : in std_logic;---48M
clkout : out std_logic;
rstout : out std_logic;
addressout : out std_logic_vector(7 downto 0);
datainout : out std_logic_vector(7 downto 0);---要写进卡里的数据
strobeout : out std_logic;
writenout : out std_logic;
spisysclk : out std_logic;
ackfrom_spimaster : in std_logic;
dataoutin : in std_logic_vector(7 downto 0);---读进来的数据
dataoutout : out std_logic_vector(7 downto 0)---读进来的数据送出去
);
end datasource;
architecture behave of datasource is
signal clkout1 : std_logic;
signal rstout1 : std_logic;
signal tmp1 :integer := 0;
signal tmp3 :integer := 0;
signal counterout : integer := 0;
--signal dataWrite : integer := 0;
signal dataWrite : std_logic_vector(7 downto 0);
signal dataWrite_integer : integer range 0 to 511;
-------------------------------------------------------
component counter
generic(counter_end : integer);
port (
clk : in std_logic;
counter_out : out integer
);
end component;
-----------------------------------------------------
procedure write_data
(
signal clkout2 : in std_logic;
signal rstout2 : in std_logic;
ackfrom_spimaster1 : in std_logic;
addressin : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
strobein :in std_logic;
writenin : in std_logic;
signal address : out std_logic_vector(7 downto 0);
signal data : out std_logic_vector(7 downto 0);
signal strobe :out std_logic;
signal writen : out std_logic
)is
begin
if rising_edge(clkout2) then
if rstout2='0' then
U5 : counterout <= 1;
--if rising_edge(clkout2) then
address <= addressin;
data <= datain;
strobe <= strobein;
writen <= writenin;
--end if;
end if;
end if;
while (ackfrom_spimaster1='0') loop
end loop;
if rising_edge(clkout2) then
U7 : counterout <= 1;
address <= "ZZZZZZZZ";
data <= "ZZZZZZZZ";
strobe <= 'Z' ;
writen <= 'Z' ;
end if;
end write_data;
--------------------------------------------------------------
--------------------------------------------------------------
procedure read_data
(
signal clkout2 : in std_logic;
signal rstout2 : in std_logic;
ackfrom_spimaster1 : in std_logic;
addressin : in std_logic_vector(7 downto 0);
signal dataout : out std_logic_vector(7 downto 0);
strobein :in std_logic;
writenin : in std_logic;
signal address : out std_logic_vector(7 downto 0);
dataspimaster_out : in std_logic_vector(7 downto 0);
signal strobe :out std_logic;
signal writen : out std_logic
)is
begin
if rising_edge(clkout2) then
if rstout2='0' then
-- if rising_edge(clkout2) then
U5 : counterout <= 1;
address <= addressin;
strobe <= strobein;
writen <= writenin;
--end if;
end if;
end if;
while (ackfrom_spimaster1='0') loop
end loop;
if rising_edge(clkout2) then
U7 : counterout <= 1;
address <= "ZZZZZZZZ";
strobe <= 'Z' ;
writen <= 'Z' ;
dataout <= dataspimaster_out;
end if;
end read_data;
---------------------------------------------------------------
begin
U1 : counter generic map(60000)
port map(clkout1,counterout);
----------------------------------------------------------
U2 : counter generic map(56000000)
port map(clkout1,counterout);
------------------------------------------------------------
U3 : counter generic map(100000)
port map(clkout1,counterout);
-------------------------------------
U4 : counter generic map(56000000)
port map(clkout1,counterout);
---------------------------------------
U5 : counter generic map(1)
port map(clkout1,counterout);
----------------------------------------------
U6 : counter generic map(1000)
port map(clkout1,counterout);
-------------------------------------------------
U7 : counter generic map(1)
port map(clkout1,counterout);
-------------------------------------------------------------
clk_generate1 : process(clk)
--variable tmp2 :integer := 0;
begin
spisysclk <= clk ;
end process;
--------------------------------------------------
clk_generate2 : process(clk)
variable tmp2 :integer := 0;
begin
if rising_edge(clk) then
tmp2:=tmp2+1;
end if;
if((tmp2 REM 2)=1) then
clkout <= '1';
clkout1 <= '1';
else
clkout <= '0';
clkout1 <= '0';
end if;
end process;
----------------------------------------
process (clkout1)
variable tmp :integer := 0;
begin
--if(clkout1 = '1') then
if rising_edge(clkout1) then
tmp:=tmp+1;
if(tmp = 8) then
rstout1 <= '1';
elsif(tmp = 9) then
rstout1 <= '0';
end if;
end if;
--writeenin <= '1';
--writeenin <= '1';
end process;
---------------------------------------
process (clkout1,rstout1)
-- variable tmp1 :integer := 0;
begin
if(tmp1 = 0) then
addressout <= "ZZZZZZZZ";
datainout <= "ZZZZZZZZ";
strobeout <= 'Z' ;
writenout <= 'Z' ;
if rising_edge(clkout1) then
if rstout1='0' then
tmp1 <= 1;
end if;
end if;
end if;
U5 : counterout <= 1;
end process;
------------------------------------------------------------
----------------------------------------------
data_test_process : process(clkout1,rstout1)
begin
U6 : counterout <= 1000;
if rising_edge(clkout1) then
if rstout1='0' then
--if rising_edge(clkout1) then
if (tmp1 = 1) then
write_data(clkout1,rstout1,ackfrom_spimaster,"00001011","00010000",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000111","01111000",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00001000","01010110",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00001001","00110100",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00001010","00010010",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000010","00000000",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000110","01011111",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000011","00000001",'1','1',addressout,datainout,strobeout,writenout);
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
--wait until dataoutin(0)='1';
while dataoutin(0)='0' loop
end loop;
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
-----------------------------------------------------------------------------------------
write_data(clkout1,rstout1,ackfrom_spimaster,"00000110","10101010",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000011","00000001",'1','1',addressout,datainout,strobeout,writenout);
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
--wait until dataoutin(0)='1';
while dataoutin(0)='0' loop
end loop;
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
------------------------------------------------------------------------------------
--init
write_data(clkout1,rstout1,ackfrom_spimaster,"00000010","00000001",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000011","00000001",'1','1',addressout,datainout,strobeout,writenout);
U1 : counterout <= 60000;
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
--wait until dataoutin(0)='1';
while dataoutin(0)='0' loop
end loop;
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
--read_data(clkout1,rstout1,ackfrom_spimaster,"00000101",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
----block write
dataWrite_integer <= conv_integer(dataWrite);
for i in 2 downto 0 loop
write_data(clkout1,rstout1,ackfrom_spimaster,"00100000",dataWrite,'1','1',addressout,datainout,strobeout,writenout);
--dataWrite <= dataWrite + '1';
--dataWrite_integer <= conv_integer(dataWrite);
--dataWrite <= dataWrite + "00000001";
dataWrite_integer <= dataWrite_integer + 1;
dataWrite <= conv_std_logic_vector(dataWrite_integer,8);
end loop;
dataWrite <= "00000000";
write_data(clkout1,rstout1,ackfrom_spimaster,"00100100",dataWrite,'1','1',addressout,datainout,strobeout,writenout);
dataWrite_integer <= conv_integer(dataWrite);
for i in 511 downto 0 loop
write_data(clkout1,rstout1,ackfrom_spimaster,"00100000",dataWrite,'1','1',addressout,datainout,strobeout,writenout);
dataWrite_integer <= dataWrite_integer + 1;
dataWrite <= conv_std_logic_vector(dataWrite_integer,8);
--dataWrite <= dataWrite + '1';
--dataWrite <= dataWrite + "00000001";
end loop;
write_data(clkout1,rstout1,ackfrom_spimaster,"00000010","00000011",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000011","00000001",'1','1',addressout,datainout,strobeout,writenout);
U2 : counterout <= 56000000;
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
--wait until dataoutin(0)='1';
while dataoutin(0)='0' loop
end loop;
----block read
write_data(clkout1,rstout1,ackfrom_spimaster,"00000010","00000010",'1','1',addressout,datainout,strobeout,writenout);
write_data(clkout1,rstout1,ackfrom_spimaster,"00000011","00000001",'1','1',addressout,datainout,strobeout,writenout);
U3 : counterout <= 100000;
U4 : counterout <= 56000000;
read_data(clkout1,rstout1,ackfrom_spimaster,"00000100",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
--wait until dataoutin(0)='1';
while dataoutin(0)='0' loop
end loop;
for i in 15 downto 0 loop
for i in 31 downto 0 loop
read_data(clkout1,rstout1,ackfrom_spimaster,"00010000",dataoutout,'1','0',addressout,dataoutin,strobeout,writenout);
end loop;
end loop;
-- end if;
end if;
end if;
end if;
end process;
-------------------------------------------
end behave;
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