count_distance.vhd

来自「基于fpga的出租车计费系统」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count_distance is
port( clkin : in std_logic;
      dip : in std_logic_vector(2 downto 0);
      clkout : out std_logic;
      length : out std_logic_vector(9 downto 0));
end entity;
architecture behav of count_distance is
  signal licheng : std_logic_vector(9 downto 0);
  signal temp0,temp1 : std_logic_vector(9 downto 0);
begin
  with dip select
    licheng<=  conv_std_logic_vector(10,10) when "000",
               conv_std_logic_vector(20,10) when "001",
               conv_std_logic_vector(30,10) when "010",
               conv_std_logic_vector(40,10) when "011",
               conv_std_logic_vector(50,10) when "100",
               conv_std_logic_vector(60,10) when "101",
               conv_std_logic_vector(70,10) when "110",
               conv_std_logic_vector(80,10) when "111";
  process(clkin,temp0,temp1)
  begin
    if rising_edge(clkin) then
      temp0<=temp0+'1';
    end if;
  end process;
  process(clkin,temp0,temp1,licheng)
  begin
    if temp0>=licheng then
      if rising_edge(clkin) then
        temp1<=temp1+'1';
      end if;
    end if;
    if temp1 =conv_std_logic_vector(5,10) then
      temp1<=(others=>'0');
    end if;
  end process;
  clkout<='1' when temp1=conv_std_logic_vector(4,10) else '0';
  length<=licheng when temp0<=licheng else temp0;
end behav;