detector.vhf

来自「一个简单的探测110三位的探测器」· VHF 代码 · 共 123 行

-- VHDL model created from detector.sch - Fri Jun 16 15:52:05 2006


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity detector is
   port ( A       : in    std_logic; 
          XLXN_50 : in    std_logic; 
          Y       : out   std_logic);
end detector;

architecture BEHAVIORAL of detector is
   attribute INIT       : STRING ;
   attribute BOX_TYPE   : STRING ;
   signal XLXN_90  : std_logic;
   signal XLXN_110 : std_logic;
   signal XLXN_149 : std_logic;
   signal XLXN_150 : std_logic;
   signal XLXN_151 : std_logic;
   signal XLXN_152 : std_logic;
   signal XLXN_153 : std_logic;
   signal XLXN_155 : std_logic;
   signal XLXN_156 : std_logic;
   signal XLXN_157 : std_logic;
   signal XLXN_163 : std_logic;
   signal XLXN_165 : std_logic;
   component FD
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C : in    std_logic; 
             D : in    std_logic; 
             Q : out   std_logic);
   end component;
   attribute INIT of FD : COMPONENT is "0";
   attribute BOX_TYPE of FD : COMPONENT is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : COMPONENT is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : COMPONENT is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : COMPONENT is "BLACK_BOX";
   
   component OR3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR3 : COMPONENT is "BLACK_BOX";
   
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : COMPONENT is "BLACK_BOX";
   
begin
   XLXI_20 : FD
      port map (C=>XLXN_50, D=>XLXN_90, Q=>XLXN_155);
   
   XLXI_21 : FD
      port map (C=>XLXN_50, D=>XLXN_110, Q=>XLXN_163);
   
   XLXI_22 : AND2
      port map (I0=>XLXN_163, I1=>XLXN_155, O=>Y);
   
   XLXI_23 : OR2
      port map (I0=>XLXN_150, I1=>XLXN_149, O=>XLXN_90);
   
   XLXI_31 : INV
      port map (I=>XLXN_163, O=>XLXN_156);
   
   XLXI_32 : INV
      port map (I=>A, O=>XLXN_165);
   
   XLXI_36 : INV
      port map (I=>XLXN_155, O=>XLXN_157);
   
   XLXI_37 : OR3
      port map (I0=>XLXN_153, I1=>XLXN_152, I2=>XLXN_151, O=>XLXN_110);
   
   XLXI_38 : AND2
      port map (I0=>XLXN_156, I1=>XLXN_155, O=>XLXN_149);
   
   XLXI_39 : AND3
      port map (I0=>A, I1=>XLXN_163, I2=>XLXN_157, O=>XLXN_150);
   
   XLXI_40 : AND3
      port map (I0=>XLXN_156, I1=>XLXN_157, I2=>A, O=>XLXN_151);
   
   XLXI_41 : AND3
      port map (I0=>XLXN_163, I1=>XLXN_155, I2=>A, O=>XLXN_152);
   
   XLXI_42 : AND3
      port map (I0=>XLXN_156, I1=>XLXN_155, I2=>XLXN_165, O=>XLXN_153);
   
end BEHAVIORAL;