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LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DECD IS PORT ( CLK : IN STD_LOGIC; DSPY : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; D :

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation

library ieee; use ieee.std_logic_1164.all; entity mux6_1 is port( sel : in std_logic_vector(2 downto 0); clk : in std_logic; datain : in std_logic_vector(9 downto 0); d

--used for key LIBRARY ieee; USE ieee.std_logic_1164.all; entity Rint is port( int1 : in std_logic; clk,rst : in std_logic; ready : in std_logic; ccs,ads,blast,wr :

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG10B IS PORT ( Load : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO

-- Project : Low Frequency Therapy -- Programmer : Byungchan Son -- Function : -- Language : VHDL --============================================================================ library ieee;

--reg_exchange.vhd --v0.1 --output measure library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity reg_exchange is port( clk: in std_logic; reset: in std_log

--conv_213.vhd (2,1,3) juan ji ma of G=(111,101) --v0.1 --06-10-2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity conv_213 is port( clk: in std_logic;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity img is port( clk_50M,rset : in std_logic; hs_out,vs_out,r_out,g_out,b_out : out std_logic; s : i

library ieee; use ieee.std_logic_1164.all; entity chuan is port ( m :in std_logic_vector (17 downto 0); x : out std_logic_vector(23 downto 0) ); end chuan; ARCHITECTURE ART