mux6_1.vhd

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library ieee;
use ieee.std_logic_1164.all;
entity mux6_1 is
port( 
      sel : in std_logic_vector(2 downto 0);
      clk : in std_logic;
      datain : in std_logic_vector(9 downto 0);
      data0 : out std_logic_vector(9 downto 0);
      data1 : out std_logic_vector(9 downto 0);
      data2 : out std_logic_vector(9 downto 0);
      data3 : out std_logic_vector(9 downto 0);
      data4 : out std_logic_vector(9 downto 0);
      data5 : out std_logic_vector(9 downto 0));

end entity;
architecture behav of mux6_1 is
begin
  process(sel,clk)
  begin
  if rising_edge(clk) then
    case sel is
         when "000" =>data0<=datain; 
         when "001" =>data1<=datain; 
         when "010" =>data2<=datain; 
         when "011" =>data3<=datain; 
         when "100" =>data4<=datain; 
         when "101" =>data5<=datain; 

         when others=>data0<="0000000000";data1<="0000000000";data2<="0000000000";data3<="0000000000";data4<="0000000000";data5<="0000000000";
      end case;
  end if;
end process;
end behav;