bus_control.vhd

low frequency therapy system control VHDL code

-- Project 		: Low Frequency Therapy
-- Programmer	: Byungchan Son
-- Function		: 
-- Language		: VHDL
--============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--============================================================================
-- 涝免仿 器飘 沥狼
--============================================================================
entity bus_control is
	port(
		-- system signal
		reset : in std_logic;
		clock : in std_logic;
		-- CPU interface
		gcs_n : in std_logic;
		we_n : in std_logic;
		oe_n : in std_logic;
		addr : in std_logic_vector(6 downto 0);
		data_in : in std_logic_vector(7 downto 0);
		data_out : out std_logic_vector(7 downto 0);
		-- pulse control
		p1_voltage : out std_logic_vector(7 downto 0);
		p1_width : out std_logic_vector(7 downto 0);
		p1_onoff : out std_logic;
		p2_voltage : out std_logic_vector(7 downto 0);
		p2_width : out std_logic_vector(7 downto 0);
		p2_onoff : out std_logic;
		p3_voltage : out std_logic_vector(7 downto 0);
		p3_width : out std_logic_vector(7 downto 0);
		p3_onoff : out std_logic;
		p4_voltage : out std_logic_vector(7 downto 0);
		p4_width : out std_logic_vector(7 downto 0);
		p4_onoff : out std_logic;
		period_flag : out std_logic;
		-- LCD
		lcd_spena : out std_logic;
		lcd_spck : out std_logic;
		lcd_spda : out std_logic;
		lcd_bright_out : out std_logic
		-- test signal
		);
end bus_control;
--============================================================================
-- 备炼 沥狼
--============================================================================
architecture bus_control_a of bus_control is
--------------------------------------------------------------------
-- 郴何 葛碘
--------------------------------------------------------------------
--------------------------------------------------------------------
-- 郴何 脚龋
--------------------------------------------------------------------
-- state machine signal
-- data signal
signal t_gcs : std_logic;
signal t1_gcs : std_logic;
signal t2_gcs : std_logic;
signal t_we : std_logic;
signal t_oe : std_logic;
signal t_addr : std_logic_vector(6 downto 0);
signal lcd_brightness : std_logic_vector(7 downto 0);
signal pwm_clock_count : std_logic_vector(11 downto 0);
signal lcd_pwm_count : std_logic_vector(7 downto 0);
-- 妻胶 林扁 惯积
signal pulse_period : std_logic_vector(7 downto 0);
signal count_5ms : std_logic_vector(19 downto 0);
signal count_period : std_logic_vector(7 downto 0);
signal p_start_flag : std_logic;
signal p_out_flag : std_logic;
--============================================================================
-- 橇肺技辑 矫累
--============================================================================
begin
	----------------------------------------------------------------
	-- 郴何 葛碘 搬急
	----------------------------------------------------------------
	----------------------------------------------------------------
	-- 妻胶 林扁 惯积扁
	----------------------------------------------------------------
	gen_period : process(
		reset,
		clock,
		count_5ms,
		count_period
		)
	begin
		if(reset = '1')then
			count_5ms <= (others => '0');
			count_period <= (others => '0');
			period_flag <= '0';
			p_start_flag <= '0';
			p_out_flag <= '0';
		elsif(clock'event and clock = '1')then
			if(count_5ms = "01111010000100100000")then
				count_5ms <= (others => '0');
				if(count_period = "00000000")then
					count_period <= pulse_period;
					period_flag <= '1';
					p_start_flag <= '1';
				else
					count_period <= count_period - 1;
				end if;
			else
				if(count_5ms = "00000000001111101000" and p_start_flag = '1')then
					p_out_flag <= '1';
					p_start_flag <= '0';
				elsif(count_5ms = "00000001111101000000")then
					p_out_flag <= '0';
				end if;
				period_flag <= '0';
				count_5ms <= count_5ms + 1;
			end if;
		end if;
	end process;
	----------------------------------------------------------------
	-- 皋牢 橇肺技辑
	----------------------------------------------------------------
	main: process(
		reset,
		clock,
		t_gcs,
		t1_gcs,
		addr,
		data_in
		)
	begin
		if(reset = '1')then
			-- stste mschine
			-- internal signal
			p1_voltage <= (others => '0');
			p1_width <= (others => '0');
			p1_onoff <= '0';
			p2_voltage <= (others => '0');
			p2_width <= (others => '0');
			p2_onoff <= '0';
			p3_voltage <= (others => '0');
			p3_width <= (others => '0');
			p3_onoff <= '0';
			p4_voltage <= (others => '0');
			p4_width <= (others => '0');
			p4_onoff <= '0';
			pulse_period <= (others => '0');
			t_gcs <= '0';
			t1_gcs <= '0';
			t2_gcs <= '0';
			t_we <= '0';
			t_oe <= '0';
			lcd_brightness <= (others => '1');
			lcd_spena <= '1';
			lcd_spck <= '1';
			lcd_spda <= '0';
			data_out <= (others => '0');
		elsif(clock'event and clock = '1')then
			t_gcs <= gcs_n;
			t1_gcs <= t_gcs;
			t2_gcs <= t1_gcs;
			t_we <= we_n;
			t_oe <= oe_n;
			t_addr <= addr;
			if(t2_gcs = '1' and t1_gcs = '0' and t_we = '0')then
				if(t_addr(5 downto 3) = "000")then
					case t_addr(2 downto 1) is
						when "00" =>
							p1_voltage <= data_in;
						when "01" =>
							p1_width <= data_in;
						when "10" =>
							pulse_period <= data_in;
						when others =>
							p1_onoff <= data_in(0);
					end case;
				elsif(t_addr(5 downto 3) = "001")then
					case t_addr(2 downto 1) is
						when "00" =>
							p2_voltage <= data_in;
						when "01" =>
							p2_width <= data_in;
						when "10" =>
							pulse_period <= data_in;
						when others =>
							p2_onoff <= data_in(0);
					end case;
				elsif(t_addr(5 downto 3) = "010")then
					case t_addr(2 downto 1) is
						when "00" =>
							p3_voltage <= data_in;
						when "01" =>
							p3_width <= data_in;
						when "10" =>
							pulse_period <= data_in;
						when others =>
							p3_onoff <= data_in(0);
					end case;
				elsif(t_addr(5 downto 3) = "011")then
					case t_addr(2 downto 1) is
						when "00" =>
							p4_voltage <= data_in;
						when "01" =>
							p4_width <= data_in;
						when "10" =>
							pulse_period <= data_in;
						when others =>
							p4_onoff <= data_in(0);
					end case;
				elsif(t_addr(5 downto 3) = "100")then
					lcd_brightness <= data_in;
				else
					lcd_spena <= data_in(2);
					lcd_spck <= data_in(1);
					lcd_spda <= data_in(0);
				end if;
			elsif(t2_gcs = '1' and t1_gcs = '0' and t_oe = '0')then
				data_out <= "0000000" & p_out_flag;
			end if;
		end if;
	end process;
	----------------------------------------------------------------
	-- LCD 灌扁 PWM 免仿
	----------------------------------------------------------------
	lcd_pwm : process(
		reset,
		clock,
		lcd_brightness,
		pwm_clock_count,
		lcd_pwm_count
		)
	begin
		if(reset = '1')then
			pwm_clock_count <= (others => '0');
			lcd_pwm_count <= (others => '0');
			lcd_bright_out <= '1';
		elsif(clock'event and clock = '1')then
			if(pwm_clock_count = "111111111111")then
				pwm_clock_count <= (others => '0');
				if(lcd_brightness = "11111111")then
					lcd_bright_out <= '1';
				elsif(lcd_pwm_count >= lcd_brightness)then
					lcd_bright_out <= '0';
				else
					lcd_bright_out <= '1';
				end if;
				lcd_pwm_count <= lcd_pwm_count + 1;
			else
				pwm_clock_count <= pwm_clock_count + 1;
			end if;
		end if;
	end process;
	----------------------------------------------------------------
	-- 肺流 脚龋
	----------------------------------------------------------------
end bus_control_a;
--============================================================================
-- 场
--============================================================================