img.vhd

VGA彩色信号控制器设计：用VHDL语言编写程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity img is
 port( clk_50M,rset : in std_logic;
       hs_out,vs_out,r_out,g_out,b_out : out std_logic;
       s : in std_logic_vector(1 downto 0));
end entity img;
architecture vhd of img is
component vga_800_600 
 port( clk : in std_logic;
       rgb_in : in std_logic_vector(2 downto 0);
       hs,vs,r,g,b : out std_logic;
       hcnt_out : out std_logic_vector(9 downto 0);
       vcnt_out : out std_logic_vector(9 downto 0));
end component;
component choose 
 port(s : in std_logic_vector(1 downto 0);
      a,b,c : in std_logic_vector(2 downto 0);
      qout : out std_logic_vector(2 downto 0));
end component;
component gepan
 port( hcnt_in,vcnt_in : in std_logic_vector(9 downto 0);
       clk,vs_in : in std_logic;
       q : out std_logic_vector(2 downto 0));
end component;
component number
 port(vs_in,clk,rset : in std_logic;
      hcnt_in,vcnt_in : in std_logic_vector(9 downto 0);
      q : out std_logic_vector(2 downto 0));
end component;
component move
 port( vs_in,clk,rset : in std_logic;
        hcnt,vcnt : in std_logic_vector(9 downto 0);
        q : out std_logic_vector(2 downto 0));
end component;
signal t4,t5,t6,t7 : std_logic_vector(2 downto 0);
signal t1,t8,t9 : std_logic;
signal t2 : std_logic_vector(9 downto 0);
signal t3 : std_logic_vector(9 downto 0);
--signal t4,t5,t6,t7,t10 : std_logic_vector(2 downto 0);
begin
u1: vga_800_600 port map(clk=>t1,rgb_in=>t7,hcnt_out=>t2,vcnt_out=>t3,hs=>hs_out,
                          vs=>t8,r=>r_out,g=>g_out,b=>b_out);
u2: choose port map(s=>s,a=>t4,b=>t5,c=>t6,qout=>t7);
u3: gepan port map (clk=>t1,q=>t4,vs_in=>t8,hcnt_in=>t2,vcnt_in=>t3);
u4: number port map (clk=>t1,vs_in=>t8,hcnt_in=>t2,vcnt_in=>t3,q=>t5,rset=>t9);
u5: move port map (clk=>t1,vs_in=>t8,hcnt=>t2,vcnt=>t3,q=>t6,rset=>t9);
t1<=clk_50M;
vs_out<=t8;
t9<=rset;
--hs_out<=t9;
end architecture vhd;