chuan.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
entity chuan is 
port (
      m :in std_logic_vector (17 downto 0);
      x : out std_logic_vector(23 downto 0)
       );
end chuan;
ARCHITECTURE ART OF chuan IS
begin
   x<="000000"&m;
end art;