rint.vhd

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

--used for key
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity Rint is port(
		int1     : in std_logic;
		clk,rst  : in std_logic;
		ready    : in std_logic;
        ccs,ads,blast,wr     : out std_logic;
        la       : out std_logic_vector(31 downto 2);
        ld       : in  std_logic_vector(31 downto 0);
        key      : buffer std_logic_vector(63 downto 0)
);
end Rint;

architecture a of Rint is
signal tint:std_logic; 
type state1 is(idle,r0,r1,r2,r3,r4,r5,r6,r7);
signal state :state1;
signal key1,key2:std_logic_vector(31 downto 0);

begin
process(rst,clk)
begin
     if rst='0' then
        ccs<='Z';ads<='Z';blast<='Z';wr<='Z';
        la(31 downto 2)<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
        key(63 downto 0)<="0000000000000000000000000000000000000000000000000000000000000000";
        --ld(31 downto 0)<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
     elsif clk'event and clk='1' then
         case state is
                when idle=>
                         ccs<='Z';ads<='Z';blast<='Z';wr<='Z';
                         la(31 downto 2)<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
                         --ld(31 downto 0)<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
                         if int1='0' then  --int1 is a one clk pulse
                             state<=r0;
                         else
                             state<=idle;
                         end if;
                when r0=>
                         ccs<='1';ads<='1';blast<='1';wr<='1';state<=r1;
                when r1=>
                         ccs<='0';ads<='0';blast<='1';wr<='0';state<=r2;
                         la(31 downto 2)<="000000000000000000000000110110";
                when r2=>
                         ccs<='1';ads<='1';blast<='1';wr<='0';state<=r3;
                when r3=>
                         state<=r4;
                when r4=>
                         if ready='0' then 
                            key1<=ld;
                            la(31 downto 2)<="000000000000000000000000110111"; 
                            blast<='0';
                            state<=r5;
                         else
                            state<=r4;end if;
                when r5=>
                         state<=r6;
                when r6=>
                         if ready='0' then 
                            key2<=ld;
                            blast<='1';
                            state<=r6;
                         else
                            state<=r7;end if; 
                when r7=>
                         state<=idle;
                         key(63 downto 32)<=key1;
                         key(31 downto 0) <=key2;
           end case;
      end if;
end process;

end a;