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找到约 10,000 项符合
Logic Analyzer 的代码
dcnt6.vhd
--DCNT6.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT6 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA:IN STD_LOGIC;
cnt10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(
CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
ENA: IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOW
cnt3.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT3 IS
PORT(
CLK:IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT:OUT STD_LOGIC );
END CN
cnt6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT(
CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
ENA: IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWN
alu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port
( br_in:in std_logic_vector(15 downto 0);
cs:in std_logic_vector(31 downto 0);
clk:in std_
pc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pc is
port
( mbr_in:in std_logic_vector(7 downto 0);--mbr[15..8]
cs:in std_logic_vector(31 downto 0);
receiver.vhd
--异步接收电路VHDL程序。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity receiver is
port (rst,clk,rxd,ERBF : in std_logic ;
dout : out std_logic_vector (7 downto 0) ;
lab9bench.vhd
---------------------------------------------------------------------------------
---- Digital Systems Design - VHDL and Programmable Logic Devices
---- Instructor: Dr. C. S. Lin
---- T.A.: Fadi
lab9bench.vhd.bak
---------------------------------------------------------------------------------
---- Digital Systems Design - VHDL and Programmable Logic Devices
---- Instructor: Dr. C. S. Lin
---- T.A.: Fadi
extcomp.vhd
--*******************************************************************--
-- Copyright (c) 1999-2000 Evatronix Ltd. --
--****************************************************