lab9bench.vhd

this is vhdl program for two address method

--------------------------------------------------------------------------------- 
----  Digital Systems Design - VHDL and Programmable Logic Devices 
----  Instructor: Dr. C. S. Lin
----  T.A.: Fadi Ali Muheidat
---------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity Lab9Bench is
  port (  input: in std_logic_vector(7 downto 0); 
  sb,sb1,sb2,sb3	: 	in std_logic;  -- Inputs
	   clk	:	in std_logic;
	   AN0, AN1, AN2, AN3,done	:	out std_logic;
        segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g, segment_dp :	out std_logic);
end Lab9Bench;

architecture Behavioral of Lab9Bench is

component AnodeControl 
port (clk	: in std_logic;  
  	   counter_out	:	out std_logic_vector (2 downto 0);
	   Anode	:	out std_logic_vector (3 downto 0));
end component;

component largest 
   port(pb1,pb2,pb,st,clk:in std_logic;
        input:in std_logic_vector(7 downto 0);
        --sum:out std_logic_vector(15 downto 0);
       number:out std_logic_vector(15 downto 0);
       done: out std_logic);-- can be sum or largest
end component;

--component binary2bcd
    --port(N: in std_logic_vector(7 downto 0);
        --pb,clk: in std_logic;
        --output: out std_logic_vector(15 downto 0);
        --done: out std_logic);
--end component;

component LEDDisplay 
  port (   number: 	in std_logic_vector(15 downto 0);	
	   counter:	in std_logic_vector(2 downto 0);
        segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g :	out std_logic);
end component;

signal counter:	std_logic_vector (2 downto 0);
signal Anode:	std_logic_vector (3 downto 0);
signal number: std_logic_vector(15 downto 0);
signal pb1,pb2,pb,st,done1:std_logic;

begin

AN0 <= Anode(0);
AN1 <= Anode(1);
AN2 <= Anode(2);
AN3 <= Anode(3);


segment_dp <= '1';
done<=done1;
pb1<=sb;
pb2<=sb1;
pb<=sb2;
st<=sb3;
--bin2bcd1:	binary2bcd port map (N,pb,clk,outputb,done1);	--clk is 50 MHz
great: largest port map (sb,sb1,sb2,sb3,clk,input,number,done1);
LEDDisplay0: 	LEDDisplay  port map (number,counter,segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g);
ANDisplay:	AnodeControl port map (clk,counter,anode);

end Behavioral;