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找到约 10,000 项符合
Logic Analyzer 的代码
img.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity img is
port(clk50mhz:in std_logic;
hs,vs,r,g,b:out std_logic);
end img;
architecture behave of img is
componen
imgrom.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity vgarom is
port ( CLK1 : in STD_LOGIC;
A18 : out STD_LOGIC;
OE1 : out STD_LOGIC;
clk: in STD_LOGIC
rs232.vhd
--
--A simple RS232 and PS/2 protocol application.
--The data received from the keyboard will be sent to
--the computer through the RS232 interface.
--And the data received from the computer will be d
tf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tf is
port(ena:in std_logic;
tclk:in std_logic;
clr:in std_logic;
tsq:buffer std_logic_v
tf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tf is
port(ena:in std_logic;
tclk:in std_logic;
clr:in std_logic;
tsq:buffer std_logic_v
bzq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bzq is
port(bena:in std_logic;
bclk:in std_logic;
clr:in std_logic;
bzq:buffer std_logic_
bzq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bzq is
port(bena:in std_logic;
bclk:in std_logic;
clr:in std_logic;
bzq:buffer std_logic_
dvf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dvf is
port (clk:in std_logic;
d:in std_logic_vector(7 downto 0);
fout:buffer std_logic);
end dv
jtd.vhd
library ieee;
use ieee.std_logic_1164.all;
entity jtd is
port(ini ,clk,spe:in std_logic;
ar,ay,ag,al:out std_logic;
br,by,bg,bl:out std_logic;
atime :out std_logic_vector(6 downto 0);
btime :ou
wishbone_i2c_master.vhd
--
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (tha