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找到约 10,000 项符合
Logic Analyzer 的代码
shaomiao.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shaomiao IS
PORT(
CP :IN STD_LOGIC;
SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SELOUT :OUT STD_LOGIC_V
zhonghe.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zhonghe IS
PORT(
CP,clr,zf,ff :IN STD_LOGIC;
SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SELOUT :OUT STD
shaomiaod.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shaomiaod IS
PORT(
CP :IN STD_LOGIC;
SEGOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SELOUT :OUT STD_LOGIC_V
tansf.vhd
library ieee;
use ieee.std_logic_1164.all;
entity tansf is
port(d1,d2,d3,d4 : in std_logic;
q : out std_logic_vector(3 downto 0));
end tansf;
architecture bb of tansf is
begin
process(d1,d2
selling.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY selling IS
PORT(
gw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
g1,d1,g2,d2
disp.vhd
library ieee;
use ieee.std_logic_1164.all;
entity disp is
port(
d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0)
);
end disp;
architecture b of disp is
begin
process
s4to1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY s4to1 IS
PORT(
gw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dw :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
d1,d2,d3,d4 :
convert.vhd
Library ieee;
USE IEEE.std_logic_1164.all;
Entity convert IS
port(a:in std_logic_vector(3 downto 0);
sel2,sel4:in std_logic;
b:out std_logic_vector(7 downto 0));
End convert;
architect
bell.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bell is
port(
q1,q2,q3,q4:in std_logic_vector(3 downto 0);
ena,reset: in std_logic;
clk: in std_logic;
dataselect.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY dataselect IS
PORT(
sel : IN STD_LOGIC_VECTOR(3 downto 0);
p0,p1,p2,p3,p4