disp.vhd

VHDL电子抢答器的实现。有多个文件

library ieee;
use ieee.std_logic_1164.all;
entity disp is 
port(
	d:in std_logic_vector(3 downto 0);
	q:out std_logic_vector(6 downto 0)
);
end disp;
architecture b of disp is
begin
	process(d)
	begin
		case d is
			when "0000"=>Q<="1111110";
			when "0001"=>Q<="0110000";
			when "0010"=>Q<="1101101";
			when "0011"=>Q<="1111001";
			when "0100"=>Q<="0110011";
			when "0101"=>Q<="1011011";
			when "0110"=>Q<="1011111";
			when "0111"=>Q<="1110000";
			when "1000"=>Q<="1111111";
			when "1001"=>Q<="1111011";
			when "1110"=>q<="0000001";
			when others=>Q<="0000000";
		END CASE;
	end process;
end b;