s4to1.vhd

VHDL电子抢答器的实现。有多个文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY s4to1 IS
PORT(
		gw	:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		dw	:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		d1,d2,d3,d4 :in std_logic_vector(3 downto 0);
        g1,g2,g3,g4 :in std_logic_vector(3 downto 0);
		s	:IN STD_LOGIC_vector(1 downto 0));

END s4to1;


ARCHITECTURE b OF s4to1 IS

BEGIN
PROCESS(s)
begin
	if s="00" then
			gw<=g1;
 			dw<=d1;
	elsif s="01" then
			gw<=g2; 
			dw<=d2; 
	elsif s="10" then
			gw<=g3;
			dw<=d3;  
	elsif s="11" then
			gw<=g4; 
			dw<=d4;
   end if;	
END PROCESS;
END b;