📄 tansf.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity tansf is
port(d1,d2,d3,d4 : in std_logic;
q : out std_logic_vector(3 downto 0));
end tansf;
architecture bb of tansf is
begin
process(d1,d2,d3,d4)
variable temp:std_logic_vector(3 downto 0);
begin
temp:=d1&d2&d3&d4;
case temp is
when "1000"=>q<="0001";
when "0100"=>q<="0010";
when "0010"=>q<="0011";
when "0001"=>q<="0100";
when others=>q<="0000";--是15不显示
end case;
end process;
end bb;
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