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Logic Analyzer 的代码
scan.vhd
--（2）显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan is
port(clk:in std_logic; ---20MHz时钟输入
a:in std_logic_vector(31 d
time.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity time is
port(clkin:in std_logic;
sp:in std_logic;
set:in std_logic;
re
compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Victor
shuma_2dt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2dt is
port(reset,en,data: in std_logic;
clk: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:
shuma_2jt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2jt is
port(data: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:out std_logic_vector(5 downto
maichong.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity maichong is
port(reset,en,data: in std_logic;
out0:out std_logic_vector(7 downto 0)
);
end maichong;
architec
shuma_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2 is
port(data: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:out std_logic_vector(5 downto 0
pe_pkg.vhd
------------------------------------------------------------------------
--
-- Copyright (C) 1998-1999, Annapolis Micro Systems, Inc.
-- All Rights Reserved.
--
--------------------------------
jianfaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jianfaqi is
port(A,B:in std_logic_vector(3 downto 0);
s: out std_logic_v
mux21w16.vhd
-- output of CoreGen module generator
-- $Header: mux2VHT.vhd,v 1.2 1998/06/15 17:57:53 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19