time.vhd

24秒倒计时系统（有跑马灯） 利用CPLD

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity time is
	port(clkin:in std_logic;
		sp:in std_logic;
		set:in std_logic;
		reset:in std_logic;
		show:out std_logic;
		t_out:out std_logic_vector(5 downto 0)
		);
end time;

architecture arc_time of time is
signal tim1:std_logic_vector(5 downto 0);
signal re1:std_logic;
signal clock:std_logic;
begin
process
begin
case tim1 is
when "000000" =>show<='1';
when others=>show<='0';
end case;
end process;

process(reset)
begin
case reset  is
when '0' => t_out<="100100";
			re1<='1';
when others=> t_out<=tim1;
			re1<='0';
end case;
end process;

process(sp)
begin
case sp is
when '1'=>clock<=set;
when others=>clock<=clkin;
end case;
end process;

process(clock,re1)
alias lcount:std_logic_vector(3 downto 0) is tim1(3 downto 0);
alias hcount:std_logic_vector(1 downto 0) is tim1(5 downto 4);
begin
if re1='1' then
	tim1<="100100";
else 
	if rising_edge(clock) then
	if lcount=0 then
		if hcount/=0 then
			lcount<="1001";
			hcount<=hcount-1;
		end if;
	else lcount<=lcount-1;
	end if;
	end if;
end if;
end process;
end arc_time;