📄 jianfaqi.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jianfaqi is
port(A,B:in std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0);
j:inout std_logic_vector(4 downto 0)
);
end jianfaqi;
architecture abc of jianfaqi is
component fullsubstractor
port(A,B,C:in std_logic;
borrow:out std_logic;
difference:out std_logic
);
end component;
begin
u0:fullsubstractor port map(A(0),B(0),j(0),j(1),s(0));
u1:fullsubstractor port map(A(1),B(1),j(1),j(2),s(1));
u2:fullsubstractor port map(A(2),B(2),j(2),j(3),s(2));
u3:fullsubstractor port map(A(3),B(3),j(3),j(4),s(3));
j(0)<='0';
end abc;
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