fullsubstractor.vhd

来自「用硬件描述语言编程实现减法器,实现两个操作数的减法」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fullsubstractor is
    port(A,B,C:in std_logic;
          borrow:inout std_logic;
          difference:out std_logic
          );
end fullsubstractor;
architecture a of fullsubstractor is
   begin
  borrow<=(not A and B)or(not A and C)or(B and C);
  difference<=A xor B xor C;
end a;