shuma_2dt.vhd

用vhdl做得CPLD静态两位数码管扫描 显示“10”两位数码管公用段选

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2dt is
port(reset,en,data: in std_logic;
clk: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:out std_logic_vector(5 downto 0)
);
end shuma_2dt;

architecture behv of shuma_2dt is
signal cnt0:std_logic_vector(3 downto 0);
signal cnt1:std_logic;
--signal indata:std_logic;
--indata<=data;

function conv(bcd_code:std_logic_vector(3 downto 0)) return std_logic_vector is
variable tmp:std_logic_vector(7 downto 0);
begin
case bcd_code is
when "1001"=>tmp:="01101111";
when "1000"=>tmp:="01111111";
when "0111"=>tmp:="00000111";
when "0110"=>tmp:="01111101";
when "0101"=>tmp:="01101101";
when "0100"=>tmp:="01100110";
when "0011"=>tmp:="01001111";
when "0010"=>tmp:="01011011";
when "0001"=>tmp:="00000110";
when others=>tmp:="00111111";
end case;
return tmp;
end function conv;

function conver(choice:std_logic) return std_logic_vector is
variable temp:std_logic_vector(5 downto 0);
begin
case choice is
when '0'=>temp:="000001";
when '1'=>temp:="000010";
when others=>temp:="000010";
end case;
return temp;
end function conver;

begin
p1:process(reset,en,clk)
begin
if(reset='1') then --复位后，计数值为0
cnt0<="0000";
cnt1<='1';
elsif rising_edge(clk) then --data的上升沿有?
if(en='1') then --当en=’1’时，允许计数
if(cnt0<"1001") then --计数采用的是BCD码加法计数器
cnt0<=cnt0+1; --个位计数
cnt1<='1';
else
 cnt0<="0000";
end if;
end if;
end if;
end process p1;

p2:process(data)
begin

 case data is
   when '0'=>cnt1<='0';cnt0<="0001";
   when '1'=>cnt1<='1';cnt0<="0000";
   when others=>null;
 end case;

 out0<=conv(cnt0);--将计数值转换为七段码，并输出到LED上显示
 out1<=conver(cnt1);
end process p2;



end behv;