maichong.vhd

来自「用vhdl做得CPLD静态两位数码管扫描 显示“10”两位数码管公用段选」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity maichong is
port(reset,en,data: in std_logic;
out0:out std_logic_vector(7 downto 0)
);
end maichong;
architecture behv of maichong is
signal cnt0:std_logic_vector(3 downto 0);
function conv(bcd_code:std_logic_vector(3 downto 0)) return std_logic_vector is
variable tmp:std_logic_vector(7 downto 0);
begin
case bcd_code is
when "1001"=>tmp:="01101111";
when "1000"=>tmp:="01111111";
when "0111"=>tmp:="00000111";
when "0110"=>tmp:="01111101";
when "0101"=>tmp:="01101101";
when "0100"=>tmp:="01100110";
when "0011"=>tmp:="01001111";
when "0010"=>tmp:="01011011";
when "0001"=>tmp:="00000110";
when others=>tmp:="00111111";
end case;
return tmp;
end function conv;
begin
process(reset,en,data)
begin
if(reset='1') then --复位后，计数值为0
cnt0<="0000";
elsif(data'event and data='1') then --data的上升沿有