scan.vhd

利用VHDL语言编写的一个蛇形的程序

--（2）显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan is
port(clk:in std_logic;                           ---20MHz时钟输入
     a:in std_logic_vector(31 downto 0);         ---蛇行状态输入
     aa:in std_logic_vector(7 downto 0);         ---圈数显示输入
     ctr:out std_logic_vector(2 downto 0);       ---3-8译码器控制端输出
     q  :out std_logic_vector(7 downto 0));      ---数码管输出
end;
architecture scan of scan is
begin
process(clk)
variable count:std_logic_vector(2 downto 0);
begin
if(clk'event and clk='1')then
    if(count="101")then
         count:=(others=>'0');
         ctr<=count;
    else count:=count+1;
         ctr<=count;
    end if;
    case count is
    when "001" => q<=a(31 downto 24);
    when "010" => q<=a(23 downto 16);
    when "011" => q<=a(15 downto 8);
    when "100" => q<=a(7 downto 0);
    when "101" => q<=aa;
    when others => q<=(others=>'0');
    end case;
end if;
end process;
end;