📄 shuma_2.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2 is
port(data: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:out std_logic_vector(5 downto 0)
);
end shuma_2;
architecture behv of shuma_2 is
signal cnt0:std_logic_vector(7 downto 0);
signal cnt1:std_logic_vector(5 downto 0);
signal indata:std_logic;
begin
indata<=data;
process(indata)
begin
cnt0<="00000110";
case indata is
when '0'=>cnt1<="000001";
when '1'=>cnt1<="000010";
when others=>null;
end case;
end process;
out1<=cnt1;
out0<=cnt0;
end behv;
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