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找到约 10,000 项符合
Logic Analyzer 的代码
vga_interface.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Vga_interface is
Port ( clk : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
comrx.vhd
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
entity ComRx is
port ( clk : in std_logic;
din :
vga.vhd
-------------------------------------------------------------------------------
-- vga.vhd
--
-- Author(s): Ashley Partis and Jorgen Peddersen
-- Created: Jan 2001
-- Last Modified: Jan
dpc.vhd
---------------------------------------------------------------------------
-- dpc (PWM generator)
---------------------------------------------------------------------------
library ieee;
use ieee.
traffic.vhd
--
-- File: E:\traffic.vhd
-- created: 09/23/04 04:55:01
-- from: 'E:\traffic.asf'
-- by fsm2hdl - version: 2.0.1.60
--
library IEEE;
use IEEE.std_logic_1164.all;
-- SYNOPSYS library decl
cnt60_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt60_2 is
port(clk:in std_logic;
s1,s0:out std_logic_vector(3 downto 0);
co:out std_logic);
end cnt60
rdff.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rdff is
generic (size : integer := 2);
port (clk,reset : in std_logic;
d : in std_logic
litenandfsm.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO