traffic.vhd

VHDL编写的交通灯程序

--
--  File: E:\traffic.vhd
-- created: 09/23/04 04:55:01
--  from: 'E:\traffic.asf'
--  by fsm2hdl - version: 2.0.1.60
--
library IEEE;
use IEEE.std_logic_1164.all;

-- SYNOPSYS library declaration
--library SYNOPSYS;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--library METAMOR;
--use METAMOR.ATTRIBUTES.all;

entity traffic is 
  port (CLK: in STD_LOGIC;
        D: in STD_LOGIC;
        N: in STD_LOGIC;
        RD: in STD_LOGIC;
        C1: out STD_LOGIC_VECTOR (3 downto 0);
        C2: out STD_LOGIC_VECTOR (3 downto 0);
        LG_1: out STD_LOGIC;
        LG_2: out STD_LOGIC;
        LR_1: out STD_LOGIC;
        LR_2: out STD_LOGIC;
        LY_1: out STD_LOGIC;
        LY_2: out STD_LOGIC);
end;

architecture traffic_arch of traffic is

-- diagram signals declarations
signal Q1: INTEGER range 0 to 50;
signal Q2: STD_LOGIC_VECTOR (3 downto 0);
signal Q3: STD_LOGIC_VECTOR (3 downto 0);
signal T11: STD_LOGIC;
signal T12: STD_LOGIC;
signal T13: STD_LOGIC;
signal T21: STD_LOGIC;
signal T22: STD_LOGIC;
signal T23: STD_LOGIC;

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (MAIN, NIGHT, START, SUB);
signal Sreg0: Sreg0_type;

begin
-- concurrent signals assignments


Sreg0_machine: process (CLK, rd)

begin

if RD='0' then
	LR_1<='0';
	LG_1<='0';
	LY_1<='0';
	LR_2<='0';
	LG_2<='0';
	LY_2<='0';
	T11<='0';
	T12<='1';
	T13<='0';
	T21<='1';
	T22<='0';
	T23<='0';
	Q1<=0;
	Q2<="0100";
	Q3<="0101";
	Sreg0 <= START;
elsif CLK'event and CLK = '1' then
	case Sreg0 is
		when MAIN =>
			LR_1<=T11;
			LG_1<=T12;
			LY_1<=T13;
			LR_2<=T21;
			LG_2<=T22;
			LY_2<=T23;
			Q1<=Q1+1;
			C1<=Q2;
			C2<=Q3;
			if Q3="0000" then 
			        Q2<=Q2-1;
			        Q3<="1001";
			elsif Q3>"0000" then 
			        Q3<=Q3-1;
			end if;
			if D='0' and N='1' then
				Sreg0 <= NIGHT;
			elsif D='0' and N='0' then
				Sreg0 <= START;
			elsif Q1>=35 and Q1<42 then
				Sreg0 <= MAIN;
				T12<=not T12;
			elsif Q1=42 then
				Sreg0 <= MAIN;
				T12<='0';
				T13<='1';
				T23<='1';
			elsif Q1=45 then
				Sreg0 <= SUB;
				T11<='0';
				T12<='1';
				T13<='0';
				T21<='1';
				T22<='0';
				T23<='0';
				Q1<=0;
				Q2<="0011";
				Q3<="0000";
			elsif D='1' and N='0' then
				Sreg0 <= MAIN;
			end if;
		when NIGHT =>
			T13<=not T13;
			LY_1<=T13;
			LY_2<=T13;
			LR_1<='0';
			LG_1<='0';
			LR_2<='0';
			LG_2<='0';
			if D='0' and N='1' then
				Sreg0 <= NIGHT;
			elsif D='1' and N='0' then
				Sreg0 <= MAIN;
			elsif D='0' and N='0' then
				Sreg0 <= START;
			end if;
		when START =>
			LR_1<='0';
			LG_1<='0';
			LY_1<='0';
			LR_2<='0';
			LG_2<='0';
			LY_2<='0';
			T11<='0';
			T12<='1';
			T13<='0';
			T21<='1';
			T22<='0';
			T23<='0';
			Q1<=0;
			Q2<="0100";
			Q3<="0101";
			if D='0' and N='0' then
				Sreg0 <= START;
			elsif D='1' and N='0' then
				Sreg0 <= MAIN;
			elsif D='0' and N='1' then
				Sreg0 <= NIGHT;
			end if;
		when SUB =>
			LR_2<=T11;
			LG_2<=T12;
			LY_2<=T13;
			LR_1<=T21;
			LG_1<=T22;
			LY_1<=T23;
			Q1<=Q1+1;
			if Q3="0000" then Q2<=Q2-1;
			Q3<="1001";
			elsif Q3>"0000" then Q3<=Q3-1;
			end if;
			C1<=Q2;
			C2<=Q3;
			if D='0' and N='0' then
				Sreg0 <= START;
			elsif D='0' and N='1' then
				Sreg0 <= NIGHT;
				T11<='0';
				T12<='1';
				T13<='0';
				T21<='1';
				T22<='0';
				T23<='0';
				Q1<=0;
			elsif Q1>=20 and Q1<27 then
				Sreg0 <= SUB;
				T12<=not T12;
			elsif Q1=27 then
				Sreg0 <= SUB;
				T12<='0';
				T13<='1';
				T23<='1';
			elsif Q1=30 then
				Sreg0 <= MAIN;
				T11<='0';
				T12<='1';
				T13<='0';
				T21<='1';
				T22<='0';
				T23<='0';
				Q1<=0;
				Q2<="0100";
				Q3<="0101";
			elsif D='1' and N='0' then
				Sreg0 <= SUB;
			end if;
		when others =>
			null;
	end case;
end if;
end process;

end traffic_arch;