rdff.vhd

组成原理的大作业

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rdff is 
   generic (size : integer := 2);
   port (clk,reset : in std_logic;
         d         : in std_logic_vector(size-1 downto 0);
         q 		   : buffer std_logic_vector(size-1 downto 0));
end rdff;
architecture archdff of rdff is
begin
p1 : process (reset,clk) begin
       if (reset='1') then
         q<= (others =>'0');
       elsif (clk'event and clk='1')then
         q<=d;
       end if;
     end process;
end archdff;