dpc.vhd

来自「This is a project about PWM. Application」· VHDL 代码 · 共 43 行

---------------------------------------------------------------------------
-- dpc (PWM generator)
---------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dpc is
  port (
    clk         : in std_logic;
    period      : in std_logic_vector(31 downto 0);
    width       : in std_logic_vector(31 downto 0);
    pulse       : out std_logic
  );
end entity;

architecture behaviour of dpc is
signal counter: std_logic_vector(31 downto 0);

begin
  process 
    begin
      wait until rising_edge(clk);

      if (counter >= period) then
        counter <= (others => '0');
      else
        counter <= counter + '1';
      end if;

      if (counter >= width) then
        pulse <= '0';
      else
        pulse <= '1';
      end if;

    end process;
end behaviour;