cnt60_2.vhd

来自「数字钟」· VHDL 代码 · 共 32 行

library	ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt60_2 is
port(clk:in std_logic;
    s1,s0:out std_logic_vector(3 downto 0);
    co:out std_logic);
end cnt60_2;
architecture behav of cnt60_2 is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
 if cnt1="0101" and cnt0="1000" then
    co<='1';
    cnt0:="1001";
elsif cnt0<"1001" then
     cnt0:=cnt0+1;
else cnt0:="0000";
  if cnt1<"0101" then
   cnt1:=cnt1+1;
else cnt1:="0000";
    co<='0';
end if;
end if;
end if;
s1<=cnt1;
s0<=cnt0;
end process;
end behav;