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Logic Analyzer 的代码
ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepe
asyrw.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:00:14 04/05/2008
-- Design Name:
-- Module Name: vhdl1 - Be
light.vhd
-----------------------------------------------------
--author: Suntion Tang
--date: 2008-6-7
-- two warning
--modify: By Suntion Tang at 2008-6-14
--description: 顶层文件，由于此系统简单，
--
cnt109.vhd
-----------------------------------------------------
--author: Suntion Tang
--date: 2008-6-7
--modify: By suntion Tang
--description: this is a counter of 106 system
---------------------
pio_rtl.vhd
-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core
mode.vhd
-----------------------------------------------------
--author: Suntion Tang Weixuan Yuan
--date: 2008-5-23
--modify: By suntion Tang
-----------------------------------------------------
jfq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity JFQ is
port (
CLKSIN,CLK,CONLINK,RESET,clk100:in std_logic;
time
xiaodou.vhd
Library ieee;
use ieee.std_logic_1164.all;
entity xiaodou is
port (
clk,a:in std_logic;
aa :OUT STD_LOGIC
);
end;
architecture behv of xiaodou is
SIGNAL C
maxout.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MAXOUT IS
PORT
( JIASHUIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
maxstartxt.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MAXSTARTXT IS
PORT( XIN,YIN : IN STD_LOGIC_VECTOR(8 DOWNTO 0);