asyrw.vhd

C6713dsp to fpga dpram,自己调试成功了

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:00:14 04/05/2008 
-- Design Name: 
-- Module Name:    vhdl1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description:  for 6713dsp's emif to read and write to the ram inside the fpga!
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity vhdl1 is
	generic (
		-- EMIF port / Port A
		NumberOfDataBits 	: integer := 16;	-- 8-bit EMIF
		NumberOfAddrBits 	: integer := 9	-- 9 Address lines for Block RAM
		-- System Port / Port B
		--NumberOfSysDataBits : integer := 32;
		--NumberOfSysAddrBits : integer := 9;
		-- Block SelectRAM
		--UsedBlockRamWidth 	: integer := 8
	);
	 port (
	     tardy: out std_logic;
	     dsprst: in std_logic;
		  flashrst: out std_logic;
        -- EMIF side
        EmifClk		: in std_logic;
        --EmifRst		: in std_logic;
        EmifAddr	: in std_logic_vector (NumberOfAddrBits-1 downto 0);
        EmifData	: inout std_logic_vector (NumberOfDataBits-1 downto 0);
        EmifSoe		: in std_logic;
        EmifCe		: in std_logic;
        EmifSwe		: in std_logic;
        EmifSads	: in std_logic
		  ----EmifAddrnotused: out std_logic
        --EmifBe		: in std_logic_vector (((NumberOfDataBits/8)-1) downto 0);
          -- Internal or system side
        --SysClk		: in std_logic;
        --SysRst		: in std_logic;
        --SysAddr		: in std_logic_vector (NumberOfSysAddrBits-1 downto 0);     -- Address can be different width.
        --SysData		: Inout std_logic_vector (NumberOfSysDataBits-1 downto 0);  -- Data can be different width.
        --SysRdWr		: in std_logic;
        --SysEna		: in std_logic_vector (((NumberOfSysDataBits/UsedBlockRamWidth)-1) downto 0)
    );


end vhdl1;

architecture Behavioral of vhdl1 is

--component instantiation--

component singleram1
port (
addr: IN std_logic_VECTOR(NumberOfAddrBits-1 downto 0);
clk: IN std_logic;
	din: IN std_logic_VECTOR(NumberOfDataBits-1 downto 0);
	dout: OUT std_logic_VECTOR(NumberOfDataBits-1 downto 0);
en: IN std_logic;
	we: IN std_logic;
	sinit :IN std_logic);
	
  end component;
  
--subtype halfword is std_logic_vector(NumberOfDataBits-1 downto 0); 
--type memory0 is array(0 to 2 ** NumberOfAddrBits-1)of halfword; ---512  byte的单口RAM

--signal   sram1 :memory0;

signal   clk : std_logic;
signal	din :  std_logic_vector (NumberOfDataBits-1 downto 0);
signal   addr : std_logic_vector (NumberOfAddrBits-1 downto 0);
signal	en :   std_logic;
signal	we :   std_logic;
signal	dout : std_logic_vector (NumberOfDataBits-1 downto 0);
signal   soe:  std_logic;
signal   sads:  std_logic;
signal   swe:  std_logic;
signal   sinit:  std_logic;	

begin 

tardy<='1';

clk<=EmifClk;

flashrst<=dsprst; 

sinit<= not dsprst;

----EmifAddrnotused<=""

	u1: singleram1 port map (clk=>clk,
	                din=>din,
                addr=>addr,
                en=>en,
                we=>we,
                dout=>dout,
					 sinit=>sinit);
		

emiftoram: process(EmifClk,EmifCe, EmifAddr, EmifSoe, EmifSwe, EmifSads) 

begin



  if (EmifClk'event and EmifClk='1') then 

	  
	  if (EmifCe='0') then en<='1';   addr<=EmifAddr; 
		soe<=EmifSoe	;	
       
		 swe<=EmifSwe	;	
       
		sads<=EmifSads;

   if (soe='0') then  we<='0';   ---read process; 
	
	if (sads='0') then EmifData<=dout; 
  
   else  EmifData<="ZZZZZZZZZZZZZZZZ";
	
	end if; 
	
	end if;
	
	if (soe='1') then   ---write process;
	
	if (swe='0') then we<='1'; din<=EmifData;
		  
		  else we<='0'; din<="ZZZZZZZZZZZZZZZZ";
	
	end if;
	
	end if; 
	

	
	else en<='0';  addr<="ZZZZZZZZZ";
	
		    soe<='Z'	;	
         swe<='Z'	;	
          sads<='Z';
        din<="ZZZZZZZZZZZZZZZZ" ;
	 EmifData<="ZZZZZZZZZZZZZZZZ";
   
	 end if;	end if;

   


end process;




end Behavioral;