light.vhd

--author: Suntion Tang --date: 2008-6-7 -- two warning --modify: By Suntion Tang at 2008-6-14 -

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--author:  Suntion Tang  
--date:    2008-6-7
--         two warning
--modify:  By Suntion Tang at 2008-6-14
--description: 顶层文件，由于此系统简单，
--             且底层文件不多，故放弃原理图描述，采用VHDL语言描述
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LIGHT IS
        PORT ( RSTC: IN STD_LOGIC;  
               CLK : IN STD_LOGIC;
               light  : OUT STD_LOGIC_VECTOR (7 downto 0)  );
END ;
ARCHITECTURE ONE OF LIGHT IS 
 COMPONENT CNT109
    PORT (CLK : IN STD_LOGIC;                     
          RST : IN STD_LOGIC;                                         
          OUTY : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );          
   END  COMPONENT;
 COMPONENT RGB 
        PORT ( CIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);  
               CLK ,RST: IN STD_LOGIC;
               outy  : OUT STD_LOGIC_VECTOR(7 downto 0)  );
END  COMPONENT;
SIGNAL TIME: STD_LOGIC_VECTOR(6 DOWNTO 0); 
BEGIN
U1:   CNT109 PORT MAP(CLK=>CLK,RST=>RSTC,OUTY =>TIME   ); 
U2:   RGB   PORT MAP(CLK=>CLK,RST=>RSTC,CIN =>TIME, outy=>light); 
END;