mode.vhd

VHDL编写的数字钟

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--author:  Suntion Tang  Weixuan Yuan
--date:    2008-5-23
--modify:  By suntion Tang
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mode IS
    PORT (modekey : IN STD_LOGIC;                                                       
          OUTY : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) );           
   END ;
ARCHITECTURE behav OF mode IS 
    SIGNAL CQI : STD_LOGIC_VECTOR(1 DOWNTO 0); 
    SIGNAL temp : STD_LOGIC_VECTOR(1 DOWNTO 0); 
BEGIN
P_REG: PROCESS(modekey,CQI) 
        BEGIN
        IF modekey'EVENT AND modekey = '1' THEN                 
                    IF CQI<2 THEN 
                    CQI <= CQI + 1;    
                    ELSE  CQI <= "00";  
                    END IF;   
                   END IF; 
       temp<=CQI;   
        END PROCESS P_REG ; 
outcon: PROCESS(temp) 
       begin
         if(temp="00") then outy<="01111";
         else if(temp="01") then outy<="01100";
         else if(temp="10") then outy<="10011";
         else outy<="01111";
      end if ;
      end if ;
      end if ;
       END PROCESS outcon ; 
END  behav;