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---------------------------------------------------------------------------------- -- Bufon, Ferluga -- Progetto elettronica 2 FPGA -- Termometro visualizzato su VGA ------------------------------

-------------------------------------------------------------------------------- -- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. -------------------------------------------------------

-------------------------------------------------------------------------------- -- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. -------------------------------------------------------

-- -- pre.vhd -- -- Cordic pre-processing block -- -- -- step 1: determine quadrant and generate absolute value of X and Y -- Q1: Xnegative -- Q2: Ynegative -- -- step 2: swap X and Y values if Y>X

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity c_k is port( CLK : in std_logic; c_out: out std_logic); end c_k; architecture c_mk of c_k is signal C

-- -- Reference design - Real Time Clock and Calendar -- -- Modified By George Wang. -- -- The design is based on 's2esk_startup' (the initial design for Spartan-3E -- Starter Kit when delivere

library ieee; use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; entity cnt is port(in_clk,en,rst: in std_logic; CQ: out std_logic_vector(3 downto 0); cout:out std_

Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity gcd is port( a,b:in std_logic_vector(7 downto 0); CLK,RST,START:in std_logic; c:ou

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FACTORIAL is port(A : in STD_LOGIC_VECTOR(3 downto 0); F :out STD_LOGIC_VECTOR(31 downto 0); ST_A,

entity overload is end overload; architecture beh of overload is Type LOGIC4 is ('0','1','Z','X'); Type L4_TWO_DIM_ARR is array(LOGIC4,LOGIC4) of LOGIC4; Type L4_ONE_DIM_ARR is