termometro.vhf

simple thermometr in vhdl

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-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2i
--  \   \         Application : sch2vhdl
--  /   /         Filename : termometro.vhf
-- /___/   /\     Timestamp : 12/02/2007 20:41:04
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx92i\bin\nt\sch2vhdl.exe -intstyle ise -family spartan2 -flat -suppress -w "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA/VGAterm/termometro.sch" termometro.vhf
--Design Name: termometro
--Device: spartan2
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity termometro is
   port ( clk      : in    std_logic; 
          cfr1     : out   std_logic_vector (3 downto 0); 
          cfr2     : out   std_logic_vector (3 downto 0); 
          cfr3     : out   std_logic_vector (3 downto 0); 
          data_out : out   std_logic_vector (7 downto 0); 
          sn_data  : out   std_logic_vector (47 downto 0); 
          onewire  : inout std_logic);
end termometro;

architecture BEHAVIORAL of termometro is
   attribute BOX_TYPE   : string ;
   signal cont           : std_logic_vector (20 downto 0);
   signal XLXN_1         : std_logic;
   signal XLXN_11        : std_logic_vector (3 downto 0);
   signal XLXN_12        : std_logic_vector (3 downto 0);
   signal XLXN_13        : std_logic_vector (3 downto 0);
   signal sn_data_DUMMY  : std_logic_vector (47 downto 0);
   signal data_out_DUMMY : std_logic_vector (7 downto 0);
   component complemento2
      port ( sign     : in    std_logic; 
             data_in  : in    std_logic_vector (7 downto 0); 
             data_out : out   std_logic_vector (7 downto 0); 
             reset    : in    std_logic);
   end component;
   
   component estrai_cifre
      port ( temp_int : in    std_logic_vector (6 downto 0); 
             seq3     : out   std_logic_vector (3 downto 0); 
             seq2     : out   std_logic_vector (3 downto 0); 
             seq1     : out   std_logic_vector (3 downto 0));
   end component;
   
   component onewire_iface
      port ( sys_clk    : in    std_logic; 
             sys_reset  : in    std_logic; 
             data_valid : out   std_logic; 
             crc_ok     : out   std_logic; 
             data       : out   std_logic_vector (7 downto 0); 
             sn_data    : out   std_logic_vector (47 downto 0); 
             dq         : inout std_logic);
   end component;
   
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component sincronismo
      port ( clk      : in    std_logic; 
             cfr1_in  : in    std_logic_vector (3 downto 0); 
             cfr2_in  : in    std_logic_vector (3 downto 0); 
             cfr3_in  : in    std_logic_vector (3 downto 0); 
             cfr1_out : out   std_logic_vector (3 downto 0); 
             cfr2_out : out   std_logic_vector (3 downto 0); 
             cfr3_out : out   std_logic_vector (3 downto 0));
   end component;
   
   component contatore21bit
      port ( clock : in    std_logic; 
             reset : in    std_logic; 
             cont  : inout std_logic_vector (20 downto 0));
   end component;
   
begin
   data_out(7 downto 0) <= data_out_DUMMY(7 downto 0);
   sn_data(47 downto 0) <= sn_data_DUMMY(47 downto 0);
   XLXI_1 : complemento2
      port map (data_in(7 downto 0)=>sn_data_DUMMY(10 downto 3),
                reset=>cont(20),
                sign=>sn_data_DUMMY(11),
                data_out(7 downto 0)=>data_out_DUMMY(7 downto 0));
   
   XLXI_3 : estrai_cifre
      port map (temp_int(6 downto 0)=>data_out_DUMMY(7 downto 1),
                seq1(3 downto 0)=>XLXN_13(3 downto 0),
                seq2(3 downto 0)=>XLXN_12(3 downto 0),
                seq3(3 downto 0)=>XLXN_11(3 downto 0));
   
   XLXI_4 : onewire_iface
      port map (sys_clk=>clk,
                sys_reset=>cont(20),
                crc_ok=>open,
                data=>open,
                data_valid=>open,
                sn_data(47 downto 0)=>sn_data_DUMMY(47 downto 0),
                dq=>onewire);
   
   XLXI_5 : GND
      port map (G=>XLXN_1);
   
   XLXI_6 : sincronismo
      port map (cfr1_in(3 downto 0)=>XLXN_13(3 downto 0),
                cfr2_in(3 downto 0)=>XLXN_12(3 downto 0),
                cfr3_in(3 downto 0)=>XLXN_11(3 downto 0),
                clk=>cont(20),
                cfr1_out(3 downto 0)=>cfr1(3 downto 0),
                cfr2_out(3 downto 0)=>cfr2(3 downto 0),
                cfr3_out(3 downto 0)=>cfr3(3 downto 0));
   
   XLXI_8 : contatore21bit
      port map (clock=>clk,
                reset=>XLXN_1,
                cont(20 downto 0)=>cont(20 downto 0));
   
end BEHAVIORAL;