58.txt

5/8分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c_k is
port( CLK : in   std_logic;
      c_out: out std_logic);
end c_k;
architecture c_mk of c_k is
signal CNT  : std_logic_vector(2 downto 0);
signal Q    : std_logic;
begin
P1:process(CLK)
begin
if CLK'event and CLK='1' then CNT <=CNT+1;
end if;
end process P1;
P2:process(CNT)
begin
if CNT="001" or CNT="011" or CNT="101" then Q<='0';
else Q<=CLK;
end if;
end process P2;
c_out<=Q;
end c_mk;


LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_ARITH.ALL;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY  fp58 IS
        PORT( rst        :    in    STD_LOGIC;
              clk       :    in  STD_LOGIC;
              clkfrq    :    out STD_LOGIC);
    END fp58;
 
 ARCHITECTURE rtl OF fp58 IS
 --  signal  d         :    STD_LOGIC_VECTOR(24 DOWNTO 0);
 --  signal  dInc        :    STD_LOGIC_VECTOR(24 DOWNTO 0);
 --  signal  dN        :    STD_LOGIC_VECTOR(24 DOWNTO 0);
   signal  d         :    STD_LOGIC_VECTOR(6 DOWNTO 0);
   signal  dInc        :    STD_LOGIC_VECTOR(6 DOWNTO 0);
   signal  dN        :    STD_LOGIC_VECTOR(6 DOWNTO 0);
   signal  clktmp    :    STD_LOGIC;

begin 
       
    process(d)             --计算增量
    begin
        --if (d(24) ='1') then
            --dInc <= "0000000000000000000011000";    --  (24)
        if(d(6) = '1') then
            dInc <= "0001100";
         else
            --dInc <= "1001010000000110110101100";    --  (24 - 14152300)
            dInc <= "1010000"; --(12 - 60);
          end if;
    end process;
    
    process(rst, clk)
    begin
        if rst = '1' then
            d <= (others => '0');
            clktmp <= '0';
        elsif clk'event and clk = '1' then
            d <= dN;
            --if d(24) = '0' then
            if(d(6) = '0') then
                clktmp <= not clktmp;
            end if;
        end if;
    end process;
    
    dN <= d + dInc;
    clkfrq <= clktmp;
    
END rtl;