gcd.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 46 行

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity gcd is
	port(	a,b:in std_logic_vector(7 downto 0);
		CLK,RST,START:in std_logic;
		c:out std_logic_vector(7 downto 0);
		DONE:out std_logic
	    );
end gcd;
architecture dataflow of gcd is
	signal x,y:std_logic_vector(7 downto 0);
	signal equal:std_logic;
	type states is(INIT,STRT,RUN,FINISH);
	signal state,next_state:states;
begin
	process(CLK,RST,NEXT_STATE)
	begin
	if(RST='1')then STATE <= INIT;
	elsif(CLK'event and CLK='1') then
		STATE<= NEXT_STATE;
	end if;
	end process;
	NEXT_STATE<= INIT   when STATE = INIT   and START = '0' else
			STRT   when STATE = INIT   and START = '1' else
			RUN    when STATE = STRT   else
			RUN    when STATE = RUN    and EQUAL = '0' else
			FINISH when STATE = RUN    and EQUAL = '1' else
			INIT   when STATE = FINISH else
			STATE;
	process(a,b,clk,rst)
	begin
		if clk'event and clk='1' then
			if state = STRT then x<=a;y<=b;equal<='0';
			elsif state=RUN then
				if    x=y then equal <='1';
				elsif x>y then x<=x-y;
				else  y<= y-x;
				end if;
			end if;
		end if; 
	end process;
	done<='1' when STATE = FINISH else '0';
	c<=y ; 
end dataflow;