ex_p3_18_factorial.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FACTORIAL is
   port(A : in STD_LOGIC_VECTOR(3 downto 0);
        F :out STD_LOGIC_VECTOR(31 downto 0);
        ST_A,RST,CLK,START: in STD_LOGIC;
        DONE : out STD_LOGIC);
end FACTORIAL;
architecture RTL of FACTORIAL is
    signal REG_A: STD_LOGIC_VECTOR(3 downto 0);
    signal Q    : STD_LOGIC_VECTOR(31 downto 0);
    signal RUN : STD_LOGIC;
begin
    A_PROC:process(RST,CLK,ST_A)
    begin
        if ST_A = '1' then REG_A <= A;
        elsif clk = '1' and clk'event then
            if RUN = '1' then
               REG_A<= REG_A - 1;
            end if;
        end if;
    end process A_PROC;
    
    RUN_PROC:process(RST,CLK,START)
    begin
        if RST = '1' then 
           RUN <= '0';
           DONE <= '0';
        elsif clk = '1' and clk'event then
            if START = '1' then
                RUN <= '1';
            end if;
            if REG_A = "0001" then
                RUN <= '0';DONE <= '1';
            end if;
        end if;
    end process RUN_PROC;
    Q_PROC:process(RST,CLK)
    begin
        if RST = '1' then 
            Q <= X"00000001";
        elsif clk = '1' and clk'event then
            if RUN = '1' then
               Q <= Q(27 downto 0) * REG_A;
            end if;
        end if;
    end process Q_PROC;
    F <= Q;
end RTL;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity FACT_TB is end FACT_TB;
architecture BEH of FACT_TB is
    signal A : STD_LOGIC_VECTOR(3 downto 0);
    signal F : STD_LOGIC_VECTOR(31 downto 0);
    signal ST_A,RST,CLK,START: STD_LOGIC:='0';
    signal DONE : STD_LOGIC;
begin
    D:entity work.FACTORIAL
       port map(A,F,
                ST_A,RST,CLK,START,DONE);
    process
    begin
        RST <= '1'; wait for 10 ns;
        RST <= '0'; wait for 10 ns;
        A <= "0101";
        ST_A <= '1';
        wait for 10 ns;
        ST_A <= '0';
        wait for 10 ns;
        for i in 1 to 25 loop
           CLK <= '1' ; wait for 50 ns;
           CLK <= '0' ; wait for 50 ns;
       end loop;
       wait;
   end process;
   START <= '1' after 50 ns, '0' after 150 ns;
 end BEH;