cnt.vhd

来自「实现由一个4位十进制数码管（含小数点）显示结果」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity cnt is
   port(in_clk,en,rst: in std_logic;
        CQ: out std_logic_vector(3 downto 0);
        cout:out std_logic);
end ;
architecture behav of cnt is
  
begin
   process(in_clk,en,rst)
  variable CQI: std_logic_vector(3 downto 0);
    begin
      if rst='1' then CQI:=(others=>'0');cout<='0';
         elsif in_clk'event and in_clk='1' then
           if en='1' then
               if CQI<9 then CQI:=CQI+1;cout<='0';
                else CQI:=(others=>'0');cout<='1';
               end if;
            end if;
       end if;
    CQ<=CQI;
   end process;
end;