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Logic Analyzer 的代码
main.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity booth is
generic(
WidthMultiplicand: integer := 16;
WidthMultiplier : integer := 16;
WidthCount : integer := 5;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mul is
generic(
WidthMultiplicand: integer := 16;
WidthMultiplier : integer := 16;
WidthCount : integer := 5
);
mod8_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mod8_1 is
port(
a: in std_logic;
b: in std_logic_vector( 7 downto 0);
c: in std_logic_vector( 7 downto 0);
s: out std_logic_vector(7 downto 0));
end
add8_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity add8_1 is
port(
a : in std_logic_vector ( 7 downto 0);
b : in std_logic;
s : out std_logic_vector (7 downto 0));
end entity;
architecture add8_1_rtl
add8_2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity add8_2 is
port(
a: in std_logic_vector(7 downto 0);
b: in std_logic;
cont: in std_logic;
si: in std_logic_vector(
gff3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity gff3 is
port(
cont: in std_logic;
a: in std_logic_vector ( 7 downto 0);
b: in std_logic_vector ( 7 downto 0);
p: in std_logic_vector ( 7 downto 0);
s
add8_2.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
entity add8_2 is
port(
a: in std_logic_vector(7 downto 0);
b: in std_logic;
cont: in std_logic;
si: in std_logic_vector(
sum32.vhd.bak
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： sum32.vhd
-- Create Date: 19:38:27 2008-05-09
-- Engineer: Kun
dds.vhd.bak
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： dds.vhd
-- Create Date: 20:20:15 2008-05-09
-- Engineer: Kun Y