add8_2.vhd

来自「application of a galois field multiplica」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;

entity add8_2 is
    port(
        a: in std_logic_vector(7 downto 0);
        b: in std_logic;
        cont: in std_logic;
        si: in std_logic_vector(6 downto 0);
        co: out std_logic_vector(6 downto 0);
        so: out std_logic_vector(7 downto 0)
    );
end entity add8_2;

architecture add8_2_rtl of add8_2 is
    begin
        co(0)<= ((a(0) and b) and cont) and si(0);
        so(0)<= (a(0) and b) xor si(0);
        
        co(1)<= ((a(1) and b) and cont) and si(1);
        so(1)<= (a(1) and b) xor si(1);
        
        co(2)<= ((a(2) and b) and cont) and si(2);
        so(2)<= (a(2) and b) xor si(2);
        
        co(3)<= ((a(3) and b) and cont) and si(3);
        so(3)<= (a(3) and b) xor si(3);
        
        co(4)<= ((a(4) and b) and cont) and si(4);
        so(4)<= (a(4) and b) xor si(4);
        
        co(5)<= ((a(5) and b) and cont) and si(5);
        so(5)<= (a(5) and b) xor si(5);
        
        co(6)<= ((a(6) and b) and cont) and si(6);
        so(6)<= (a(6) and b) xor si(6);
        
        so(7)<= a(7) and b;
        
end architecture add8_2_rtl;