gff3.vhd

application of a galois field multiplication and normal multiplication

library ieee;
use ieee.std_logic_1164.all;

entity gff3 is
port(
cont: in std_logic;
a: in std_logic_vector ( 7 downto 0);
b: in std_logic_vector ( 7 downto 0);
p: in std_logic_vector ( 7 downto 0);
s: out std_logic_vector ( 15 downto 0));
end entity gff3;

architecture gff3_rtl of gff3 is
signal c0, c1,c2,c3,c4,c5,c6,c7: std_logic_vector (7 downto 0);
signal c,cc : std_logic_vector (15 downto 0);
signal ss1,ss2,ss3,ss4,ss5,ss6: std_logic_vector ( 7 downto 0);
signal s1, s2, s3, s4, s5, s6, s7: std_logic_vector (7 downto 0);
signal co1,co2,co3,co4,co5,co6,co7:std_logic_vector(6 downto 0);
signal ss,sss: std_logic_vector(  15 downto 0);
signal cco0,cco1,cco2,cco3,cco4,cco5,cco6,s_0,s_1,s_2,s_3,s_4,s_5,s_6: std_logic;

component add8_1 is
port(
a : in std_logic_vector ( 7 downto 0);
b : in std_logic;
s : out std_logic_vector (7 downto 0));
end component;

component add8_2 is
    port(
        a: in std_logic_vector(7 downto 0);
        b: in std_logic;
        cont: in std_logic;
        si: in std_logic_vector(6 downto 0);
        co: out std_logic_vector(6 downto 0);
        so: out std_logic_vector(7 downto 0)
    );
end component;

component add8_3 is
    port(
    a: in std_logic_vector( 7 downto 0);
    b: in std_logic;
    cont: in std_logic;
    ci: in std_logic_vector(6 downto 0);
    si: in std_logic_vector(6 downto 0);
    co: out std_logic_vector(6 downto 0);
    so: out std_logic_vector(7 downto 0));
end component;

component mod8_1 is
port(
a: in std_logic;
b: in std_logic_vector( 7 downto 0);
c: in std_logic_vector( 7 downto 0);
s: out std_logic_vector(7 downto 0));
end component;

component mod_teil is
    port(
    a: in std_logic_vector( 15 downto 0);
    p: in std_logic_vector( 7 downto 0);
    s: out std_logic_vector( 15 downto 0));
end component;

component hadder is
   port (
            a  : in  std_logic;
            b  : in  std_logic;
            s  : out std_logic;
            co : out std_logic
         );
end component;

component fadder is --full-adder
   port (
            a  : in  std_logic;
            b  : in  std_logic;
            ci : in  std_logic;
            s  : out std_logic;
            co : out std_logic
         );
end component;

begin
--Um C zu rechnen;
add8_1_1: add8_1 port map ( a, b(0), c0);
add8_2_2: add8_2 port map ( a, b(1), cont, c0(7 downto 1),co1, c1);
add8_2_3: add8_3 port map ( a, b(2), cont, co1,c1(7 downto 1),co2, c2);
add8_2_4: add8_3 port map ( a, b(3), cont, co2,c2(7 downto 1), co3, c3);
add8_2_5: add8_3 port map ( a, b(4), cont, co3,c3(7 downto 1), co4, c4);
add8_2_6: add8_3 port map ( a, b(5), cont, co4,c4(7 downto 1), co5,c5);
add8_2_7: add8_3 port map ( a, b(6), cont, co5,c5(7 downto 1), co6,c6);
add8_2_8: add8_3 port map ( a, b(7), cont, co6,c6(7 downto 1), co7, c7);

hadder8_0 : hadder port map ( c7(1), co7(0), s_0, cco0);
fadder8_1 : fadder port map ( c7(2), co7(1), cco0,s_1,cco1);
fadder8_2 : fadder port map ( c7(3), co7(2), cco1, s_2,cco2);
fadder8_3 : fadder port map ( c7(4), co7(3), cco2,s_3,cco3);
fadder8_4 : fadder port map ( c7(5), co7(4), cco3,s_4,cco4 );
fadder8_5 : fadder port map ( c7(6), co7(5), cco4,s_5,cco5 );
fadder8_6 : fadder port map ( c7(7), co7(6), cco5, s_6,cco6);

sss <= cco6 & s_6 & s_5 & s_4 & s_3 & s_2 & s_1 & s_0 & c7(0) &c6(0) & c5(0) & c4(0) & c3(0) & c2(0) & c1(0) & c0(0);

c <= c7(6) & c7 & c6(0) & c5(0) & c4(0) & c3(0) & c2(0) & c1(0) & c0(0);
--module
mod8_1_1 : mod8_1 port map (cc(14),p,cc(13 downto 6),s1);

ss1 <= s1(6 downto 0) & cc(5);
mod8_1_2 : mod8_1 port map (s1(7),p,ss1, s2);

ss2 <= s2(6 downto 0) & cc(4);
mod8_1_3 : mod8_1 port map (s2(7),p,ss2,s3);

ss3 <= s3(6 downto 0) & cc(3);
mod8_1_4 : mod8_1 port map (s3(7),p,ss3,s4);

ss4 <= s4(6 downto 0) & cc(2);
mod8_1_5 : mod8_1 port map (s4(7),p,ss4,s5);

ss5 <= s5(6 downto 0) & cc(1);
mod8_1_6 : mod8_1 port map (s5(7),p,ss5,s6);

ss6 <= s6(6 downto 0) & cc(0);
mod8_1_7 : mod8_1 port map (s6(7),p,ss6,s7);

ss<= "00000000" & s7;



process(c, ss, sss, cont)
    begin
        if cont= '1' then
            s<= sss;
            cc<="0000000000000000";
        else
           cc<=c;
           s<=ss;
        
       end if;    
    end process;
    
    
    
    


end architecture gff3_rtl;