add8_1.vhd

来自「application of a galois field multiplica」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;

entity add8_1 is
port(
a : in std_logic_vector ( 7 downto 0);
b : in std_logic;
s : out std_logic_vector (7 downto 0));
end entity;

architecture add8_1_rtl of add8_1 is
begin
s(0) <= b AND a(0);
s(1) <= b AND a(1);
s(2) <= b AND a(2);
s(3) <= b AND a(3);
s(4) <= b AND a(4);
s(5) <= b AND a(5);
s(6) <= b AND a(6);
s(7) <= b AND a(7);
end architecture add8_1_rtl;