sum32.vhd.bak

用VHDL书写的DDS程序 里面有详细的注解

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-- Project Name：  DDS_Project
-- File Name：	   sum32.vhd
-- Create Date:    19:38:27 2008-05-09
-- Engineer:	   Kun Yue
-- Target Device:  
-- Tool versions:  QuartusII 7.2
-- Description:    32位累加器
-- Additional Comments:   	
--				   k[31..0]----输入信号		en----使能信号		
--			       reset----复位信号		out1[31..0]----输出信号		
--			       clk----时钟信号
-- Revision: V1.0
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum32 is
   port(k: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        en:in std_logic;
        reset:in std_logic;
        out1:out std_logic_vector(31 downto 0));
end entity sum32;
architecture art  of sum32 is
	signal temp:std_logic_vector(31 downto 0);
	begin
	process(clk,en,reset) is
		begin 
		if reset='1'then
		temp<="00000000000000000000000000000000";
		else
		if clk'event and clk='1'then
			if en='1'then
			temp<=temp+k;
			end if;
		end if;
	end if;
	out1<=temp;
end process;
end architecture art;