dds.vhd.bak

用VHDL书写的DDS程序 里面有详细的注解

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-- Project Name：  DDS_Project
-- File Name：	   dds.vhd
-- Create Date:    20:20:15 2008-05-09
-- Engineer:	   Kun Yue
-- Target Device:  
-- Tool versions:  QuartusII 7.2
-- Description:    DDS顶层文件
-- Additional Comments:   	
--						k[31..0]----输入信号		en----使能信号		
--			      		reset----复位信号		out1[31..0]----输出信号		
--			      		clk----时钟信号
-- Revision: V1.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
	port(phaseword: in std_logic_vector(31 downto 0);--phase word 
         freword: in std_logic_vector(31 downto 0);  --frequency word
         clk:in std_logic;
         en:in std_logic;
         reset:in std_logic;
         da_data:out std_logic_vector(9 downto 0));
end entity dds;
architecture art  of dds is
-------------------------------------------------
-------------------sum32-------------------------
component sum32 is
	port(k: in std_logic_vector(31 downto 0);
         clk:in std_logic;
         en:in std_logic;
         reset:in std_logic;
         out1:out std_logic_vector(31 downto 0));
end component sum32;
-------------------------------------------------
-------------------reg1--------------------------
component reg1 is
	port(d: in std_logic_vector(31 downto 0);
         clk:in std_logic;
         q:out std_logic_vector(31 downto 0));
end component reg1;
-------------------------------------------------
-------------------adder32-----------------------
component adder32 is
	port(a: in std_logic_vector(31 downto 0);
         n: in std_logic_vector(31 downto 0);
         clk:in std_logic;
         en:in std_logic;
         out2:out std_logic_vector(31 downto 0));
end component adder32;
-------------------------------------------------
-------------------reg2--------------------------
component reg2 is
	port(e: in std_logic_vector(31 downto 0);
         clk:in std_logic;
         p:out std_logic_vector(31 downto 0));
end component reg2;
-------------------------------------------------

-------------------component5--------------------
component romtab is
	port(inclock         : in  std_logic;
		 phase_address   : in  std_logic_vector (9 downto 0); --phase address value
		 q : out std_logic_vector (9 downto 0));--wave sin value
end component romtab;         
-------------------------------------------------

signal s1:std_logic_vector(31 downto 0);
signal s2:std_logic_vector(31 downto 0);
signal s3:std_logic_vector(31 downto 0);
signal s4:std_logic_vector(31 downto 0);
signal s5:std_logic_vector(9 downto 0);
s5<=s4(31 downto 22);

begin

u1:sum32 	port map(k=>freword,en=>en,reset=>reset,clk=>clk,out1=>s1);
u2:reg1		port map(d=>s1,clk=>clk,q=>s2);
u3:adder32  port map(a=>s2,en=>en,clk=>clk,n=>phaseword,out2=>s3);
u4:reg2 	port map(e=>s3,clk=>clk,p=>s4);
u5:romtab 	port map(inclock=>clk,phase_address=>s5,q=>da_data);
end architecture art;