main.vhd

vhdl程序 Uncomment the following lines to use the declarations that are provided for instantiating Xi

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
port (
	enable_hack		: in std_logic;
	enable_skip		: in std_logic;	
	clk				: in std_logic;
	ds_clk			: in std_logic;
	cart_clk			: out std_logic;
	ds_romcs			: in std_logic;
	cart_romcs		: out std_logic;
	ds_rst			: in std_logic;
	cart_rst			: out std_logic;
	ds_eecs			: in std_logic;
	cart_eecs			: out std_logic;
	ds_data			: inout std_logic_vector(7 downto 0);
	cart_data			: inout std_logic_vector(7 downto 0);
	leds				: buffer std_logic_vector(7 downto 0) := "00000000"
	);
end main;





architecture Behavioral of main is


 -- polynomial: (0 2 15 16)
  -- data width: 8
  -- convention: the first serial data bit is D(7)
  function nextCRC16_D8  
    ( Data:  std_logic_vector(7 downto 0);
      CRC:   std_logic_vector(15 downto 0) )
    return std_logic_vector is

    variable D: std_logic_vector(7 downto 0);
    variable C: std_logic_vector(15 downto 0);
    variable NewCRC: std_logic_vector(15 downto 0);

  begin

    D := Data;
    C := CRC;

    NewCRC(0) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor 
                 D(1) xor D(0) xor C(8) xor C(9) xor C(10) xor C(11) xor 
                 C(12) xor C(13) xor C(14) xor C(15);
    NewCRC(1) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor 
                 D(1) xor C(9) xor C(10) xor C(11) xor C(12) xor C(13) xor 
                 C(14) xor C(15);
    NewCRC(2) := D(1) xor D(0) xor C(8) xor C(9);
    NewCRC(3) := D(2) xor D(1) xor C(9) xor C(10);
    NewCRC(4) := D(3) xor D(2) xor C(10) xor C(11);
    NewCRC(5) := D(4) xor D(3) xor C(11) xor C(12);
    NewCRC(6) := D(5) xor D(4) xor C(12) xor C(13);
    NewCRC(7) := D(6) xor D(5) xor C(13) xor C(14);
    NewCRC(8) := D(7) xor D(6) xor C(0) xor C(14) xor C(15);
    NewCRC(9) := D(7) xor C(1) xor C(15);
    NewCRC(10) := C(2);
    NewCRC(11) := C(3);
    NewCRC(12) := C(4);
    NewCRC(13) := C(5);
    NewCRC(14) := C(6);
    NewCRC(15) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor 
                  D(1) xor D(0) xor C(7) xor C(8) xor C(9) xor C(10) xor 
                  C(11) xor C(12) xor C(13) xor C(14) xor C(15);

    return NewCRC;

  end nextCRC16_D8;




signal iscommand : std_logic := '0';
signal cmdcount : std_logic_vector(2 downto 0);
signal datacount : std_logic_vector(11 downto 0);
signal cmdchk : std_logic_vector(7 downto 0);
signal crc16 : std_logic_vector(15 downto 0);
signal crcdata : std_logic_vector(7 downto 0);
begin
 	cart_clk <= ds_clk;
	cart_romcs <= ds_romcs;
	cart_rst <= ds_rst;
	cart_eecs <= ds_eecs;

	leds <= "00000000";

	process(ds_clk,cart_data)
	begin
		ds_data <= (others => 'Z');
		cart_data <= (others => 'Z');

		if ds_rst = '1' then
			if ds_eecs = '0' then
				cart_data(7) <= ds_data(7);
				ds_data(6) <= cart_data(6);
			end if;

			if ds_romcs = '0' then
				if iscommand ='0' then
					if enable_hack = '1' and cmdchk = "00000000" then
						-- need to replace 0x34 through 0x37 with "0x08000000"
						if datacount = "000000110100" then
							crcdata <= "00000000";
						elsif datacount = "000000110101" then
							crcdata <= "00000000";
						elsif datacount = "000000110110" then
							crcdata <= "00000000";
						elsif datacount = "000000110111" then
							crcdata <= "00001000";

						-- a little cheat, to make boot faster
						elsif datacount = "000000011111" and enable_skip = '1' then
							crcdata <= "11111111";
					
						-- need to replace 0x15E through 0x15F with the crc16 of 0x0 through 0x15D
						elsif datacount = "000101011110" then
							crcdata <= crc16(8) & crc16(9) & crc16(10) & crc16(11) & crc16(12) & crc16(13) & crc16(14) & crc16(15);
							--leds <= crc16(11 downto 4);
						elsif datacount = "000101011111" then
							crcdata <= crc16(0) & crc16(1) & crc16(2) & crc16(3) & crc16(4) & crc16(5) & crc16(6) & crc16(7);
						else
							crcdata <= cart_data;
							
						end if;
						ds_data <= crcdata;
					else
						ds_data <= cart_data;
					end if;
				else
					cart_data <= ds_data;
				end if;
			end if;
		end if;
	end process;
--	leds <= iscommand & datacount(3 downto 0) & cmdcount;
	process(ds_clk,ds_romcs)
	begin
		if ds_romcs = '1' then
			iscommand <= '1';
			cmdcount <= "000";
			cmdchk <= "00000000";
		elsif ds_clk'event and ds_clk='1' then
			if cmdcount = "111" then
				iscommand <= '0';
				datacount <= "000000000000";
				crc16 <= "1111111111111111";	
			--	crc16 <= "0000000011111000";
			end if;

			if iscommand = '1' then
				cmdcount <= cmdcount + "001";
				cmdchk <= cmdchk or ds_data;
			else
				datacount <= datacount + "000000000001";
				if datacount = "000101011110" then
			--		crc16 <= crc16;
				else
					crc16 <= nextCRC16_D8( crcdata(0) & crcdata(1) & crcdata(2) & crcdata(3) & crcdata(4) & crcdata(5) & crcdata(6) & crcdata(7), crc16 );
				end if;
			end if;
		end if;
	end process;


end Behavioral;