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找到约 10,000 项符合 Logic Analyzer 的代码

加法器描述.txt

-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------

相应加法器的测试向量（test bench).vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------

mul2.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:40:44 04/07/08 -- Design Name: -- Module Name: mul2 - B

vgacore.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vgacore is Port ( clk : in std_logic; reset : in std_logic;

qpsk.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity qpsk is port( ClkxCI : in std_logic; ResetxRBI : in std_logic; DataInxDI : in std_logic_vector

decode1.vhd

------------------------------------------------------------- --Copyright (C), 2004- , Huangwei. -- --File name:decode1(解码器) -- --Auth

test.vhd

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity test is port( reset, clk : in std_logic; datin : in std_logic_vector( 9 downto 0 ); datout : out std_logic_v

clkregen.vhd

--********************************************************************************-- -- -- -- Clock regeneration from

hdb3dec.vhd

--********************************************************************************-- -- -- -- HDB3 Decoder

avr_core.vhd

--************************************************************************************************ -- Top entity for AVR core -- Version 1.11 -- Designed by Ruslan Lepetenok -- Modified 03.11.200