vgacore.vhd

VHDL书写VGA源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vgacore is
    Port ( clk : in std_logic;
       reset : in std_logic;
           md : in std_logic_vector(1 downto 0);
           hs : out std_logic;
           vs : out std_logic;
           r : out std_logic_vector(1 downto 0);
           g : out std_logic_vector(2 downto 0);
           b : out std_logic_vector(2 downto 0)
 );
end vgacore;

architecture Behavioral of vgacore is
signal sysclk : std_logic;
signal hsyncb : std_logic;
signal vsyncb : std_logic;
signal enable : std_logic;
signal hloc : std_logic_vector(9 downto 0);
signal vloc : std_logic_vector(9 downto 0);
signal rgbx,rgby,rgbp,rgb: std_logic_vector(7 downto 0);

--定义VGASIG元件，产生同步信号进行行、场扫描，即显示驱动
component vgasig    
   Port (
       clock : in std_logic;
       reset : in std_logic;
       hsyncb : buffer std_logic;
       vsyncb : out std_logic;
       enable : out std_logic;
       Xaddr : out std_logic_vector(9 downto 0);
       Yaddr : out std_logic_vector(9 downto 0)
  );
end component;

--定义colormap元件，确定颜色及位置信息
component colormap 
   Port (
       hloc : in std_logic_vector(9 downto 0);
       vloc : in std_logic_vector(9 downto 0);
       rgbx : out std_logic_vector(7 downto 0);
       rgby : out std_logic_vector(7 downto 0)
  );
end component;

begin
  rgb(7) <= rgbp(7) and enable;
  rgb(6) <= rgbp(6) and enable;
  rgb(5) <= rgbp(5) and enable;
  rgb(4) <= rgbp(4) and enable;
  rgb(3) <= rgbp(3) and enable;
  rgb(2) <= rgbp(2) and enable;
  rgb(1) <= rgbp(1) and enable;
  rgb(0) <= rgbp(0) and enable;

--产生25Mhz的像素输出频率
  divclk: process(clk,reset)
  begin
    if reset='0' then
     sysclk <= '0';
  elsif clk'event and clk='1' then
    sysclk <= not sysclk;
  end if;
  end process;
  
--模式选择单元：本测试程序我们使用了4种模式，由KEY_B2,KEY_B3控制，
--当选择模式"11"时，即不按下B2，B3，VGA显示竖彩条；当选择模式"00"时，
--即同时按下B2，B3时，VGA显示全黑；当选择模式"01"时，即只按下B2时，VGA显示横彩条；
--当选择模式"10"时，即只按下B3时，VGA时显示横竖彩条。
  modchoice: process(md,rgbx,rgby)
  begin
    if md="11" then rgbp <= rgbx;
  elsif md="01" then rgbp <= rgby;
  elsif md="10" then rgbp <= rgbx xor rgby;
    else rgbp <= "00000000";
  end if;
  end process;

  makesig: vgasig Port map(
       clock => sysclk,
       reset => reset,
       hsyncb => hsyncb,
       vsyncb => vsyncb,
       enable => enable,
       Xaddr => hloc,
       Yaddr => vloc
  );

  makergb: colormap Port map(
       hloc => hloc,
       vloc => vloc,
       rgbx => rgbx,
       rgby => rgby
  );

  hs <= hsyncb;
  vs <= vsyncb;
  r <= rgb(7 downto 6);
  g <= rgb(5 downto 3);
  b <= rgb(2 downto 0);
   
end Behavioral;