clkregen.vhd

来自「HDB3编解码」· VHDL 代码 · 共 63 行

--********************************************************************************--
--                                                                                --
--  Clock regeneration from the input HDB3 line code                              --
--                                                                                --
--********************************************************************************--


library IEEE;
use IEEE.std_logic_1164.all;


entity clkregen is
	port
	(
		sgnlx : in std_logic ;
		sgnly : in std_logic ;
		reset : in std_logic ;
		clk : in std_logic ;
		clk2m : out std_logic 
	);
begin
end clkregen ;


architecture structure of clkregen is 
	signal code : std_logic ;
	signal edge : std_logic ;
	signal count : std_logic_vector(3 downto 0) ;
	signal temp : std_logic_vector(1 downto 0) ;
	signal five : std_logic_vector(3 downto 0) ;

	component cnt4
	port
		(
		p : in std_logic_vector(3 downto 0) ;
    		clk : in std_logic ;
		reset : in std_logic ;
	        load : in std_logic ;
    		q : out std_logic_vector(3 downto 0) 
		) ;
	end component ; 

begin
    
	u1 : cnt4
        	port map(p=>five,clk=>clk,reset=>reset,load=>edge,q=>count);

	process(reset, clk)
	begin
		if (reset='0') then
			temp<="00";
		elsif (clk'event) and (clk='0') then
			temp(0)<=code ;
			temp(1)<=temp(0) ;
		end if ;
	end process ;
	
	five<="0101" ;
	code<=sgnlx xor sgnly ;
	edge<=temp(0) and (not temp(1)) ;
	clk2m<=count(3) ;
end structure ;